Power minimization

[kp1998_]

Hello

For a verilog code, how can post synthesis power be reduced.

Thanks

Regards

Neha

[anunesgu]

Hi @kp1998_,

Please take a look at the document https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug907-vivado-power-analysis-optimization.pdf which contains all the instructions and options for power optimization in Vivado.

Thanks,