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Participant
Participant
477 Views
Registered: ‎06-11-2019

Power minimization

Hello

For a verilog code, how can post synthesis power be reduced.

Thanks

Regards

Neha

 

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1 Reply
Moderator
Moderator
395 Views
Registered: ‎02-09-2017

Hi @kp1998_,

 

Please take a look at the document https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug907-vivado-power-analysis-optimization.pdf which contains all the instructions and options for power optimization in Vivado.

 

Thanks,

Andre Guerrero

Product Applications Engineer

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