06-21-2016 07:23 AM
I have an external interface to block design. Say a vid_io interface. It connects to a Xilinx IP which has vid_io interface. So I am unable to connect an ILA to probe the signals.
The below discussion says expand the ports. But the external port interface does not expand to the sub-ports.
How to I probe the signals in vid_io interface ?
06-21-2016 01:02 PM
Instead of manually inserting an ILA like that (I never ever do that, personally), just right-click the net or bus and select 'Mark Debug.' This will automatically insert the ILA and it will show up when you go to set up the debugger post-synth.
06-22-2016 02:21 AM
I tried that also. When the bitstream is loaded on to the fpga
"ERROR: [Labtools 27-1973] Mismatch between the design programmed into the device xc7z020 (JTAG device index = 1) and the probes file debug_nets.ltx. The device core at location user chain=1 index=0, has 5 ILA Input port(s), but the core in the probes file has 9 ILA Input port(s)."
It is kind of a stalemate. Any help is much appreciated!
06-22-2016 02:30 AM
It seems you tried changing the number of signals probed to ILA
Please go through http://www.xilinx.com/support/answers/66860.html
06-22-2016 03:57 AM
06-22-2016 04:15 AM
Please attach the .ltx file.
Also can you please try opening implemented design and use
write_debug_probes -force filename.ltx
06-22-2016 05:36 AM
ERROR: [Labtools 27-1973] Mismatch between the design programmed into the device xc7z020 (JTAG device index = 1) and the probes file debug_nets.ltx. The device core at location user chain=1 index=0, has 5 ILA Input port(s), but the core in the probes file has 8 ILA Input port(s).
Attached is the debug_nets.ltx
06-22-2016 05:45 AM
Which version of Vivado are you using?
Is it possible to check in latest version of the tool?
Also can you please share the design file?
06-22-2016 07:15 AM
This error means the bitstream you programmed into the device is not the same one that you put the debug nets into. I will see this message if, for example, I insert my debug probes in Vivado and generate a bitstream but forget to export it to SDK. Then when I download the stale .bit from SDK and then open the Vivado GUI to look at the traces (which uses the new debug.ltx), the error will occur.
06-23-2016 01:14 AM
Sorry, sharing the src code is not an option right now. I am generating the bitstream in Vivado 2016.1 and remotely connecting hardware manager to a lab PC which is on 2015.3. I reduced the JTAG clock freq to the minimun and ensured clocks are free running.
I am not using SDK. Steps I follow are
1) open the block design
2) Mark video_io interface for debug
4) Setup debug on synthesized netlist
5) Generate bitstream
6) Verify timestamps of both debug_nets.ltx and .bit files and load both to a Zynq fpga connected remotely
Am I missing something ?
06-27-2016 02:59 AM
I've just faced the same issue.
Project is made in 2016.2.
When I try to debug in 2015.3 - error occurs.
But after upgrading debug machine to 2016.2 - it dissappears.