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Observer
Observer
9,206 Views
Registered: ‎04-11-2016

Probe interface ports

Hello,

 

I have an external interface to block design. Say a vid_io interface. It connects to a Xilinx IP which has vid_io interface. So I am unable to connect an ILA to probe the signals.

 

The below discussion says expand the ports. But the external port interface does not expand to the sub-ports.

https://forums.xilinx.com/xlnx/board/crawl_message?board.id=OTHER&message.id=7382

 

How to I probe the signals in vid_io interface ?

 

Many thanks,

Pujyan

 

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11 Replies
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Xilinx Employee
Xilinx Employee
9,183 Views
Registered: ‎08-02-2011

Re: Probe interface ports

Hello Pujyan,

 

Instead of manually inserting an ILA like that (I never ever do that, personally), just right-click the net or bus and select 'Mark Debug.' This will automatically insert the ILA and it will show up when you go to set up the debugger post-synth.

www.xilinx.com
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Observer
Observer
9,147 Views
Registered: ‎04-11-2016

Re: Probe interface ports

Hello @bwiec,

 

I tried that also. When the bitstream is loaded on to the fpga

 

"ERROR: [Labtools 27-1973] Mismatch between the design programmed into the device xc7z020 (JTAG device index = 1) and the probes file debug_nets.ltx. The device core at location user chain=1 index=0, has 5 ILA Input port(s), but the core in the probes file has 9 ILA Input port(s)."

 

https://forums.xilinx.com/xlnx/board/crawl_message?board.id=OTHER&message.id=9493

 

It is kind of a stalemate. Any help is much appreciated!

 

-Pujyan

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Moderator
Moderator
9,143 Views
Registered: ‎07-01-2015

Re: Probe interface ports

Hi @sampujyan,

 

It seems you tried changing the number of signals probed to ILA

Please go through http://www.xilinx.com/support/answers/66860.html

Thanks,
Arpan
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Observer
Observer
9,136 Views
Registered: ‎04-11-2016

Re: Probe interface ports

hi @arpansur @bwiec

 

thanks for the pointer. But the problem still persists. Only 5 out of 9 ports remain in the bitstream. Tcl command report_debug_core shows all 9 ports!

 

Is there any way to know which ports are optmized away ?

 

-Pujyan

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Moderator
Moderator
9,132 Views
Registered: ‎07-01-2015

Re: Probe interface ports

Hi @sampujyan,

 

Please attach the .ltx file.

Also can you please try opening implemented design and use 

write_debug_probes -force filename.ltx

 

Thanks,
Arpan
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Observer
Observer
9,123 Views
Registered: ‎04-11-2016

Re: Probe interface ports

hi @arpansur

 

ERROR: [Labtools 27-1973] Mismatch between the design programmed into the device xc7z020 (JTAG device index = 1) and the probes file debug_nets.ltx.  The device core at location user chain=1 index=0, has 5 ILA Input port(s), but the core in the probes file has 8 ILA Input port(s).

 

Attached is the debug_nets.ltx

 

-Pujyan

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Moderator
Moderator
9,119 Views
Registered: ‎07-01-2015

Re: Probe interface ports

Hi @sampujyan,

 

Which version of Vivado are you using?

Is it possible to check in latest version of the tool?

 

Also can you please share the design file?

 

 

Thanks,
Arpan
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Xilinx Employee
Xilinx Employee
9,109 Views
Registered: ‎08-02-2011

Re: Probe interface ports

This error means the bitstream you programmed into the device is not the same one that you put the debug nets into. I will see this message if, for example, I insert my debug probes in Vivado and generate a bitstream but forget to export it to SDK. Then when I download the stale .bit from SDK and then open the Vivado GUI to look at the traces (which uses the new debug.ltx), the error will occur.

www.xilinx.com
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Observer
Observer
9,073 Views
Registered: ‎04-11-2016

Re: Probe interface ports

@arpansur

 

Sorry, sharing the src code is not an option right now. I am generating the bitstream in Vivado 2016.1 and remotely connecting hardware manager to a lab PC which is on 2015.3. I reduced the JTAG clock freq to the minimun and ensured clocks are free running.

 

@bwiec

I am not using SDK. Steps I follow are

 

1) open the block design

2) Mark video_io interface for debug

3) Synthesize

4) Setup debug on synthesized netlist

5) Generate bitstream

6) Verify timestamps of both debug_nets.ltx and .bit files and load both to a Zynq fpga connected remotely

 

Am I missing something ?

 

 

-Pujyan

 

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Participant
Participant
7,037 Views
Registered: ‎09-10-2012

Re: Probe interface ports

I've just faced the same issue.

Project is made in 2016.2.

When I try to debug in 2015.3 - error occurs.

But after upgrading debug machine to 2016.2 - it dissappears.

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Observer
Observer
5,759 Views
Registered: ‎04-11-2016

Re: Probe interface ports

Thanks for sharing @g.pavlikh. I got around by moving the hw to my desk :)

 

 

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