cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
shirley_yang
Observer
Observer
656 Views
Registered: ‎05-12-2016

Problem when using edif file to implement a TMR Design

Hi everyone,

 

I suppose to implement a TMR design on Virtex4 board. However, there is such little information about Xilinx TMR tools online. It would be great if someone could give me some tips about TMR implementation and verification.

 

For testing and verification purpose I tried to triplicate only a submodule of my whole design (import ngc. file of the submodule to tmr tool and select Design Module option in process settings). With tmr tool a edif. file of the triplicated submodule would be created and exported to ISE. However, NgdBuild:604 error appears when I translated the xtmr design. 

 

The error: " A pin name misspelling can cause this, a missing edif or ngc
file, case mismatch between the block name and the edif or ngc file name, or
the misspelling of a type name."

 

I have modified the port map and the declaration part of the submodule (triplication of all in/out ports) to adapt to the tmr design. But it doesn't work. But if i choose to triplicate the entire design (import ngc. file of the top level design to tmr tool and select top-level FPGA option in process settings) the tmr design works. So I'm not sure if I just can't implement the submodule tmr in ISE or I missed something import?

 

I'm looking forward to your replies. And thanks a lot for your help!

0 Kudos
0 Replies