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mlf
Visitor
Visitor
2,629 Views
Registered: ‎09-01-2014

Problem with Virtex-7 VC7203 IBERT Getting Started Guide (UG847)

Hello,

 

I am trying to run the "Virtex-7 VC7203 IBERT Getting Started Guide (UG847)", as I'll need to use the GTX transceivers in a future project. I am using Vivado 2015.1 and the version 2015.1 of the UG847. I am following the UG step by step. The only difference is that I am using Q113 instead of Q115. Consequently, I had to set the SYSACE-2 CFG switch (SW8) accordingly: ADR2, ADR1 and ADR0 equal to ON. After setting up Vivado, programming the board (using the .bit and .ltx files for Q113 obtained from Xilinx webpage), starting the SuperClock-2 Module (setup_scm2_156_25.tcl script) and creating the Serial I/O Links, the status of "COMMON_X1Y0" PLL appears as "Not Locked" and the status of the MGTs is "No Link". This way, I am not able to view the GTX Transceiver operation.

 

I even tried some of the suggestions shown in the UG to overcome this situation (increase TX differential swing, TX reset and BERT reset), but none of them work. I also checked the output of the TCL console (attachment: "tcl_console_msgs.txt"), but i didn't notice any anomaly. 

 

I am new to this board and have no previous experience in working with GTX transceivers. Any help, comments or hints would be valuable.

Thanks for your attention!

Best Regards,

Mário

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venkata
Moderator
Moderator
2,399 Views
Registered: ‎02-16-2010

Since you are new to use the board, please use the default design to start with.

Please read ug476 to get the basic understanding of GTX transceivers.

When you change the GT quad, you will need to ensure the refclk location is set to the correct pins.

Since you changed the quad, have you adjusted the bull eye cable connectivity on the board?

Are you sure that the refclk is connected correctly from super clock module to the quad you intend to test?

What is the status of "LOL" LED on super clock module?
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