08-24-2013 10:35 AM - edited 08-24-2013 10:36 AM
I have talked with an FAE about this issue with ChipScope for MicroBlaze in Vivado, and below is his response:
"[After talking with a] Vivado Logic Debug expert, and unfortunately Vivado Logic Debug does not currently have the equivalent of ChipScope AXI Monitor, which is currently not supported in Vivado. Theoretically, you can do the same thing as ChipScope AXI Monitor with Vivado Logic Debug by setting up a VIO and using tcl scripts to send AXI packets that you can then probe. The user interface is missing, but the capability is all there. In the future, depending on interest, Xilinx may come out with a similar solution as ChipScope AXI Monitor, but until then this is being left to the customer.
Unfortunately, as Xilinx does not support using ChipScope cores in Vivado, the only thing I can tell you is to remove the core from PlanAhead prior to migration and then re-add a Vivado Logic Debug core per UG908 link below: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_2/ug908-vivado-programming-debugging.pdf "
My project is a MicroBlaze based design that is built in Vivado (as of now). In the Vivado design, the MicroBlaze component is the only source other than the VHD Wrapper file that encompasses the MicroBlaze component. Is it possible to instantiate the newer version of ILA (v 2.X) for any VHDL IP that we add to the MicroBlaze component?
We have tried a version of this project in Vivado without any ILAs or ChipScope Peripherals, and the design builds fine. We would just like to be able to attach ILAs to the custom IPs that we create so that we can debug them as we implement them into the design and begin to test the various IPs of the MicroBlaze component through Application Projects in SDK.
Is the message I received from the FAE correct? I have a design that successfully implemented in Vivado that was imported from PlanAhead with ChipScope AXI Monitors in the MicroBlaze component, but I never see anything in the Analyzer tool for the Monitors after I program the FPGA...it appears as though they were in fact trimmed from the design.
08-27-2013 11:03 AM
Does anyone know more about this topic to help clarify it for me? Thanks!
09-06-2013 07:40 AM
09-11-2013 05:02 AM
The information from the FAE is correct. We have an expert looking over this thread.
He will add some more information.