Scripting ILA into a mixed TCL flow

[mphanav]

Hello,

I have an existing tcl script to build my project that uses both project & non-project based commands to implement the design. In the past this has worked to complete the build process but I would like to add an ILA to the design. I have created the ILA IP .xci file and in the build process generate the output product to use in synthesis. I then import the ILA files via "import_files" and use "synth_design" to start the synthesis process. Note that the ILA is correctly instantiated in the top level file. Here is a snippet of the tcl build script that I use:

create_project -force -part xcku025-ffva1156-2-i test_project test_project
source -notrace $project_path/proc.tcl
#

source -notrace $project_path/aurora_64b66b_0_2018_2.tcl
#Add the rest of the design rtl
source -notrace $project_path/project_cfg.tcl
#
# Read Timing Constraints file
read_xdc -unmanaged $project_path/project_timing.xdc
#
# Import ILA IP and output products
import_files ../ip/ila/ila_0.xci
#
# Turn off some of the non-helpful messages
source -notrace ../tcl/suppress.tcl
#

puts ""
puts "-----------------------------------------------------------"
puts "Running synthesis on $top_level"
puts "-----------------------------------------------------------"
synth_design -top dm_top_level -directive Default -verilog_define C_TEST_AURORA_ON -verilog_define C_INCLUDE_ILA
opt_design
write_checkpoint -force dcp/syn

Here are the output messages for the build:

Starting Logic Optimization Task

Phase 1 Generate And Synthesize Debug Cores

INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub

INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.

The following Error logs belongs to dbg_hub

ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified

ERROR: [IP_Flow 19-3805] Failed to generate and synthesize debug IPs.

error copying "c:/Users/10294/ILA_SR_PREP/ILA_SR_PREP_modified/build/.Xil/Vivado-32740-EC3260/dc_drv.0/dc/prj_ip.runs/dbg_hub_synth_1/dbg_hub.dcp": no such file or directory

ERROR: [Chipscope 16-330] Synthesis of Debug Cores has failed

Phase 1 Generate And Synthesize Debug Cores | Checksum: 1b4d8ef07

Time (s): cpu = 00:00:00 ; elapsed = 00:00:48 . Memory (MB): peak = 1454.129 ; gain = 0.000

INFO: [Common 17-83] Releasing license: Implementation

8 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered.

opt_design failed

ERROR: [Chipscope 16-338] Implementing debug Cores failed due to earlier errors

INFO: [Common 17-206] Exiting Vivado at Fri Jul 17 15:20:54 2020...

What are the correct commands to properly include the ILA in the synthesized netlist? What is the recommended flow to achieve this?

Thanks.

[travisc · Accepted solution]

Do you set the following param to false in your script somewhere? 

set_param project.compositeFile.enableAutoGeneration 0

This parameter controls generation of composite files. If set to false, this stops auto generation of composite files (IP/BD) and could be the reason why ILA debug IP is failing in synthesis.

[kevinm]

travisc, many thanks for your help, that was indeed the issue.

Early in my script, aurora_64b66b_0_2018.2.tcl is executed which builds the Aurora IP. This is a script we have used successfully for some time, however I did not create it and was not aware that it was setting the project.compositeFile.enableAutoGeneration parameter. To be honest, even if I did, I would have had no clue that could have caused the problem.

Anyway, I modified my script to add the following line immediately before I call opt_design..

set_param project.compositeFile.enableAutoGeneration 1

The script now runs to the end without error.

I have taken the result all the way through to generating the .bin file and have tested it on my board and confirmed that the ILA is present and working.

Thank you

[dabaichui_]

How to set this parameter ？

set_param project.compositeFile.enableAutoGeneration 1