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Participant
Participant
262 Views
Registered: ‎03-25-2020

Simulating block design

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Hi Team,

How we can Simulate the Block Design in Vivado.

Whether required to generate test bench separately for this.

how to do so,

Please provide the Procedure to do Simulation.

With regards,

Ratheesh

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Xilinx Employee
Xilinx Employee
187 Views
Registered: ‎02-27-2019

回复: Simulating block design

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Just treat Block Design as a normal HDL file, not need special steps for it. You can Create the HDL Wrapper and instantiate it in your Testbench.Capture.PNG

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Highlighted
Xilinx Employee
Xilinx Employee
188 Views
Registered: ‎02-27-2019

回复: Simulating block design

Jump to solution

Just treat Block Design as a normal HDL file, not need special steps for it. You can Create the HDL Wrapper and instantiate it in your Testbench.Capture.PNG

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Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post