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lorenrus
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Registered: ‎10-02-2020

Simulation on Vivado

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Hi guys

i'm doing some tests with vhdl and vivado. I made a simple mux.
Within the architecture I used a "process".

From the theory I know that the assignments placed within the process are sequential to each other.

Having said that, I don't get the timing diagram of the simulation, attached. What I expected is that the output on DOUT would be at least slightly out of phase with respect to the "Sel" signal and the "Data_In".

Then I thought that it is normal that it is so because it is an ideal case and not a real one since the simulation was not done physically on an FPGA.

Is what I said correct or am I doing something wrong?

Thank you

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drjohnsmith
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Registered: ‎07-09-2009

Its correct ,

  but, as has been pointed out, free range VHDL is a start book, 

      and its a while since I have seen where my printed version is.

Also as has been said, 

   you will quickly move on from these definitions, 

     Its like when you come on to state machines,

    in class we will teach you 1, 2 and 3 process state machines, mealy and Moore , 

       and in reality, you will only ever us a single process state machine, and never worry about mealy / moore .

Sorry

   till there is a better book thats so cost effective, its the best we can offer.

 

 

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bruce_karaffa
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Registered: ‎06-21-2017

This is a behavioral simulation.  Hardware delays are not modeled except for certain Xilinx primitives where the delays are built into the models.  While you have coded the mux as a priority logic decoder, the synthesizer will just make some logic to select the output.  I think the synthesizer can do this code in 4 LUTs.  There is nothing sequential about this. 

lorenrus
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Registered: ‎10-02-2020

Hello and thanks for the reply.

So the sequencing of the assignments doesn't just depend on how the VHDL code is implemented, right?

Can you give me an example that I can create with Vivado in which instead I can appreciate the sequentiality of the assignments placed within the process?

You told me "you have coded the mux as a priority logic decoder", are there any other ways to represent it?

I attach the schematic and the code of the testbench.

 

Many thanks 

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richardhead
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Registered: ‎08-01-2012

Im not quite sure what you are asking. Your code can only ever assign one value to data_out based on the value of "sel" - there is nothing that can be sequential about it.

There is plenty you can do with VHDL in which the sequential natural a of the code changes the circuit, but that usually occurs with variables rather than signals. But in VHDL, nothing you can do with a variable for a synthesisable circuit cannot alsoo be done with a signal. It might be easier if you ask a more specific question aboout what yoou're trying to understand.

 

 

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lorenrus
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Registered: ‎10-02-2020

Hello and thanks for the reply.

My problem was exactly at the source, as you rightly say "Your code can only ever assign one value to data_out based on the value of" sel "- there is nothing that can be sequential about it". In fact, just before your answer I was thinking precisely about this aspect, in fact in the HW that I have represented there is nothing sequential.

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lorenrus
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I also wanted to add another reflection. This type of circuit described by me being completely combinatorial, to describe it I could also use a modeling of the "Data-Flow" type. Correct ? Thank you

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richardhead
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Registered: ‎08-01-2012

VHDL is a Hardware Descriptioon Language. So the user should understand what circuit they are describing before they write the code.

lorenrus
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Registered: ‎10-02-2020

Yes is correct, but my last message :"This type of circuit described by me being completely combinatorial, to describe it I could also use a modeling of the "Data-Flow" type" is this a correct consideration? Thank you 

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richardhead
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Registered: ‎08-01-2012

Please describe what you understand as "data flow type". Data always flows in an fpga.

lorenrus
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From the VHDL theory I know that I can model an architecture in three ways:

- BEHAVIOURAL
- DATA FLOW
- STRUCTURAL

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richardhead
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Registered: ‎08-01-2012

Those meanings are generally meaningless and you would often have code that matches all of those descriptions in any design. No designers use those phrases in real life and often only seen by students learning from (often very old) learning resources.

Today, it is far better to write meaningful code that is easy to read rather than stick to a regimented style fitting into any of those descriptions

 

drjohnsmith
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Registered: ‎07-09-2009

Are you self learning or in a class with others  / teacher ?

As said above, students are IMHO , often taught very abstract ideas, 

    and they often loose the fact they are designing hardware,

You also show the simulator,

     you must remember that pre synthesis , the simulator is working with just your code, it has no idea how long each data path is, they are all set at one delta. so you will not see gate / routing delays in the simulator.

 

Can I also highlight, that when you synthesise your code, the compiler will take your code and optimise it, to fit within your timming / space constraints, then stop,

    This is similar to what you might be used to in say a C compiler, your C code is optimised into the actual operating code, but unlike a C complier, the fpga synthesiser will only work till its met your space / timing constraints.

and finally , if your after a book, try this 

http://freerangefactory.org/pdf/df344hdh4h8kjfh3500ft2/free_range_vhdl.pdf

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
lorenrus
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Registered: ‎10-02-2020

I'm studying on the same book

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lorenrus
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Registered: ‎10-02-2020

In this book “free range vhdl” there is a description of architecture like I explain.

So is not correct ? Thank you 

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lorenrus
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Ok but a student from some base has to leave. I have used / am using the book that drjohnsmith also recommended.
Can you recommend a more current book? Thank you

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drjohnsmith
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Teacher
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Registered: ‎07-09-2009

Its correct ,

  but, as has been pointed out, free range VHDL is a start book, 

      and its a while since I have seen where my printed version is.

Also as has been said, 

   you will quickly move on from these definitions, 

     Its like when you come on to state machines,

    in class we will teach you 1, 2 and 3 process state machines, mealy and Moore , 

       and in reality, you will only ever us a single process state machine, and never worry about mealy / moore .

Sorry

   till there is a better book thats so cost effective, its the best we can offer.

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

lorenrus
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Registered: ‎10-02-2020
Perfect, thanks for your patience.
richardhead
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Registered: ‎08-01-2012

With the internet as it is today, writing a book is fairly pointless and would never pay itself back, plus there is plenty of plagerised material online. Plus, while the language and tools get updated, the books do not.

Once you have a basic grasp of the language, I highly recommend a basic reference book, and IMO the Doulos Golden Reference Guide is the best out there (there are some older versions illegally online - Doulos currently not selling it due to covid)

From there, maybe you could be adventuroous and then use the LRM as a reference. This would keep you up to date, and allow you to question Xilinx why VHDL feature X is not available in Vivado (please, pester them)