12-21-2018 11:17 AM
Dear Xilinx team and forum users,
we want to use the XVC interface as described in XAPP1251 with a Zynq and searching through the forum i found some reports of not working functionality.
Some threads suggest that there are, e.g.
I've read the application note, but find the information not very clear, especially when reading the XVC webpage entry and forum posts.
To not run into issues late into the design i would like to clarify whether it is supported to use a Zynq based board with Vivado 2017.4 to perform the following actions over XVC:
Load bitstream into configured/unconfigured Artix/Kintex/Spartan-7 that is
... the only element of the JTAG chain (1)
... element of a JTAG chain consisting of two or more 7-series FPGAs (2)
Load bitstream via indirect programming into standard/dual/quad SPI flash connected to Artix/Kintex/Spartan-7 that is
... the only element of the JTAG chain (3)
... element of a JTAG chain consisting of two or more 7-series FPGAs (4)
Debug Artix/Kintex/Spartan-7 using ILA with
... single element chain (5)
... chain of multiple 7-series FPGAs (6)
Same Questions but for older FPGA generations like Spartan 6 (7)
I see no technical reasons why there should be a difference to JTAG over USB as XVC is implementating JTAG on a very low level (which i like).
Aside from software bugs the only other technical reason might be timing issues, but JTAG isn't time sensitive on a "frame" basis and from my experience USB can be worse than ethernet.
Could somebody who uses one of these features share some of his experiences?
Thanks in advance.
01-22-2019 09:06 AM
There's one question that I can answer with certainty at this point, which is none of this will work for older FPGA generations like Spartan 6 (or older).
Regarding the other questions, it looks like it would work, but we would need to better understand your architecture to make that affirmation with certainty.
Could you please detail a bit more what is your use case? Where are these boards that will be configured/debugged via XVC?
I consulted with other colleagues about it, and one of the first question that came up is "can they just use the SmartLynq cable instead"? So that's a good point to exercise.
Finally, could you please share a block diagram or detail how you would be connecting the Zynq and the other boards together?
01-25-2019 05:55 AM
The design to distribute the JTAG signals is not final, we are considering to use a SCANSTA112 in transparent mode or to use a discrete solution with CMOS buffers and switches.
But this shouldn't matter from the Zynq's point of view as it only sees data coming back from the last TDO output.
I'm not sure what further information to provide, but i tried to make a block diagram. We basically use the common design for JTAG and (Q)SPI configuration flash. The electrical layer is the same as with any other choice of programmer.
Our use cases are debugging with ILA, writing preliminary bitstreams directly into different 7-Series FPGAs and also writing a new bitstream into their corresponding configuration flash through indirect programming. The bitstream of the Zynq itself will be changed via
cat bitstream.bit > /dev/xdevcfg
The SmartLynq is a great piece of equipment and I'm a very big fan of it (AV. We already use the Zynq in our design as it is needed for other functionality and also the additional space/cost make it impossible to use the SmartLynq in production design.
From your answer i read that question (7) has to be answered with "not possible", is that because of the limited support for older generations in Vivado?
Is there further information about the limitations of XVC?
Another forum post suggests that you guys are working on a newer/extended application note, which would make at least one old man very happy.