02-20-2018 08:09 AM
I have a System ILA block in my Zynq design that Im using to monitor an AXI4 interface
Usually when I use this block, the ILA waveform that shows up in the HW manager groups the signals nicely into the various AXI channels (read, write, address, response etc)
However, lately Im finding this not to be the case. Instead the waveform displays the signals without this grouping. It also misses off some of the signals, specifically the r/wvalid, r/wready signals
Any suggestion on how I can resolve this?
Using Vivado 2017.2
02-20-2018 08:23 AM
@alangford Yes, I got this from time to time as well. Not sure what causes it.
I usually delete the <project>.hw directory inside the project folder and re-open the project.
02-20-2018 01:17 PM
02-20-2018 01:28 PM
@travisc To Xilinx's defense I believe it has to do with some backup tools I have. Sometimes antivirus.
Just that Vivado relies on consistent behavior of the filesystem and when that does not happen 100%, things get dangling.
I use to wipe out the <project>.cache and <project>.runs folders regularly (every other week) for that reason.
02-21-2018 07:41 AM
Glad to hear Im not the only one who's seen this.
I haven't managed to pin-down a way to reproduce this problem.
I did however rebuild my project from scratch (tcl based build script) and the first time I fired up the hardware manager the waveform for the system ILA was in the "un-grouped" style; In-fact it also seems that none of the signals in the trace are toggling
Some background: My project is driving traffic out to DDR3 memory connected to the PL and the PS. Im using the Axi Performance Monitor to view the throughput/latency of the AXI transactions in SDK using the Performance Analysis tool.
I have a system ILA connected to the AXI bus between the traffic generator and the MIG. For sanity, I also added a regular ILA on the same bus.
My flow goes like this: Open SDK and start the performance analysis. This configures the device with the bit stream. I see the AXI transactions showing up in the performance monitor.
I then move over to the Vivado HW manager and open the target. This automatically pulls up the ILA and VIO windows
The regular ILA connected to the traffic-generator shows the signals are toggling. The System-ILA on the same bus show no activity, is missing the valid/ready signals and is not grouped into AXI channel.
This flow was working just fine for me a few days ago.
I tried the suggestion of closing the project, deleting the .hw folder and then re-opening the project, but this didn't reinstate the files in this folder so I wasnt able to see any of the data from the VIOs or ILAs
02-21-2018 07:54 AM
02-22-2018 01:29 PM
Please also try to open the synthesized (or implemented) design and run the command write_debug_probes –force C:/Your_Path/designProbes.ltx to get the LTX regenerated.
Please save that in a different path and use it along with the bitstream when programming the board.
Sometimes the LTX file gets generated after you run implementation and some net optimization might have happened, which causes the buses to be split or renamed.
Please let us know if that works.
02-22-2018 02:31 PM
@anunesgu One thing I never understood is why sometimes Vivado creates TWO ltx files. I think Vivado gets stuck on the old one and ignores the newer.
02-23-2018 03:29 AM
None of your suggestions are working for me.
I should clarify that my flow includes SDK as Im using the PS on the Zynq-7000 to use the output of the performance monitor
The ILA uses clocks from the PS. If I program the device from the Vivado HW manager my ILAs/VIOs dont show up because the clocks from the PS aren't running. I therefore have to program the device from SDK and start an application to get the clocks running. If I then switch over to Vivado and open the HW manager, the ILAs and VIOs show up automatically.
Im going to start a new simple project and add a system ILA to try to get to the bottom of this