07-07-2014 09:41 AM
I am having an issue with the Tandem PCIe stage 1 operation. I have successfully programmed the stage 1 tandem PCIe image to the PROM on the KC705, following the process outlined in Xilinx document pg054 Tandem PCIe. The board appears to configure correctly "the done led turns green. When I try this in my PC it power cycles. I believe this is related to this particular PROM image as other PCIe designs have worked.
I am using Vivado 2014.2 design envirement.
Any help with this problem would be much appreciated.
07-07-2014 09:51 PM
07-14-2014 10:09 AM
Thanks for the feed back
But I believe I am meeting the 100 ms init. time requirement.
My .bit file is 864 K bytes in size, and if I understand it correctly using the parallel PROM at 66 MHz I should load in ~7 Ms = 864 K / 66 MHz * 2
Also I have loaded significantly larger non Tandem designs 4.12 Meg byte and the PCIe operates fine.
I am using design outlined in Xilinx document pg054 Tandem PCIe
Any help on this problem wound be much appreciated.