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Adventurer
Adventurer
8,719 Views
Registered: ‎07-27-2011

Tandem PCIe causing PC to power cycle

I am having an issue with the Tandem PCIe stage 1 operation. I have successfully programmed the stage 1 tandem PCIe image to the PROM on the KC705, following the process outlined in Xilinx document  pg054 Tandem PCIe. The board appears to configure correctly "the done led turns green. When I try this in my PC it power cycles. I believe this is related to this particular PROM image as other PCIe designs have worked.

I am using Vivado 2014.2 design envirement.

 

Any help with this problem would be much appreciated.  

 

 

Thanks

 

John

 

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2 Replies
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Xilinx Employee
Xilinx Employee
8,711 Views
Registered: ‎08-01-2008

Re: Tandem PCIe causing PC to power cycle

You need to meet the 100 ms initialization time requirement?

 

 
Assuming non-ATX Power Supply
Assuming 100 Mhz clock +/- 100 ppm
Assume that the FPGA power supplies ramp to a stable level 2 ms after the 3.3V and 12V system power supplies. This time difference is called Tfpga_pwr. In this case, because the FPGA supplies ramp after the system supplies, the power supply ramp time will take away from the 100 ms margin.
 
Config time = Tpor + Load time for first stage Tandem + Tfpga_pwr
 
Tpor times - See DS
 
Load time for first stage config
 
Conservative estimate based off K325T design
 
690T Globals: 3.5 Mbit
690T PCIe : 8.25 Mbit
690T Total : 11.75 Mbit
10% buffer : ~13 Mbit
 
Load time = 13 Mbit/(8 bit Data width*99.99 MHz) = 16.25 ms
 
Max numbers based on PCIe Gen3 example design
 
26.4 Mbit
 
Load time = 26.4 Mbit/(8 bit Data width*99.99 MHz) = 33 ms
 
Best Case
 
Assuming 1 ms ramp on power to reduce POR times to 35 ms.
 
16.25 ms + 35 ms + 1 ms = 51.25 ms
 
Worst Case
 
50 ms + 33 ms + 2 ms = 85 ms
Thanks and Regards
Balkrishan
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Adventurer
Adventurer
8,684 Views
Registered: ‎07-27-2011

Re: Tandem PCIe causing PC to power cycle

Thanks for the feed back

 

But I believe I am meeting the 100 ms init. time requirement.

 

My .bit file is 864 K bytes in size, and if I understand it correctly using the parallel PROM at 66 MHz I should load in ~7 Ms = 864 K  / 66 MHz * 2

 

Also I have loaded significantly larger non Tandem designs 4.12 Meg byte and the PCIe operates fine.

 

I am using design outlined in Xilinx document  pg054 Tandem PCIe

 

Any help on this problem wound be much appreciated.

 

Thanks

 

John

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