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Adventurer
Adventurer
3,438 Views
Registered: ‎08-26-2013

Vivado 2017.2 Set as Top Option Problem

Hi,

I'm using Vivado 2017.2 in Win7 64bit. My Code consists of a vhdl module written by user and an ip core provided by Xilinx Vivado tool and of course a .xdc file. My problem is that mentioned ip core is top module without any assignment by user and the vhdl code is under Non-module files with a frozen "set as top" option. Refreshing hierarchy and the other tries war failed during troubleshooting. Is there any suggestion for this case?

 

Best Regards

mhmontazeri61

VivadoB.jpg
6 Replies
Moderator
Moderator
3,425 Views
Registered: ‎09-15-2016

Re: Vivado 2017.2 Set as Top Option Problem

Hi @mhmontazeri61,

 

Is there any unsupported or syntax issues in the .vhd file?

 

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Adventurer
Adventurer
3,404 Views
Registered: ‎08-26-2013

Re: Vivado 2017.2 Set as Top Option Problem

I don't know. Is this a new option or tool property in the new Vivado? In the previous versions and of course in Xilinx ISE, this issue was not a problem at all. How can i track unsupported or syntax issues without behavioral simulation?
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Moderator
Moderator
3,379 Views
Registered: ‎09-15-2016

Re: Vivado 2017.2 Set as Top Option Problem

Hi @mhmontazeri61,

 

Generally the non-module files display those files that produce issues during parsing.

Can you share the .vhd file in community?

 

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3,244 Views
Registered: ‎11-17-2017

Re: Vivado 2017.2 Set as Top Option Problem

I also have the question.I use the vivado 2016.2.

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Visitor jeff2177
Visitor
2,439 Views
Registered: ‎07-05-2018

Re: Vivado 2017.2 Set as Top Option Problem

I had same problem with Vivado 2018.1

 

I solved my problem. Vivado don't lets you set the top module depending on the syntaxe of your VHDL...

 

for example

my_generate: for J in (0 to 9) generate

...

 

save it and you can't have top module any more !

just remove the parenthesis around the range

 

my_generate: for J in 0 to 9 generate

 ...

 

save it

and all will come back in order.

 

same effect with loop...

if this can helps someone.

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Newbie bconant
Newbie
2,265 Views
Registered: ‎05-25-2018

Re: Vivado 2017.2 Set as Top Option Problem

I just stumbled onto this with Vivado 2017.3, so they haven't fixed their parser in that version.  Hopefully Xilinx will notice this and improve their parser.  If the generate with parenthesis is a syntax error, it should say so, rather than clobbering the hierarchy and failing to mention why.

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