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Observer inflector
Observer
6,180 Views
Registered: ‎08-29-2017

Vivado Debug Core not found ... tried suggestions here already

I've been getting an error trying to use an ILA core with a slower clock. I have a 400Khz clock running i2c I'm using to output to an LCD device. I can't easily capture any i2c communication because the bus operates at such a slow rate.

Nothing seems to work as a clock for the ila except using the built-in 100 Mhz clock available on my Arty Artix board. If I use any other clock, I get:

WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3403] Dropping logic core with cellname:'u_ila_0' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-3403] Dropping logic core with cellname:'arty_board_ila' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-3403] Dropping logic core with cellname:'controller/i2c_bus/i2c_ila' from probes file, since it cannot be found on the programmed device.


1) I first tried to use a clock that I generated with a counter internally every 250 ticks of the 100 Mhz clock.

2) Then I tried an IP clock wizard generated clock to create an 8 Mhz clock. Faster than I wanted but only 5 times, not the current 250 times faster, so I would have been able to collect 50 times as much data as with a 100 Mhz clock.

clk_wiz_0 slow_clock(
.clk_8Mhz(clock_slow),
.reset(reset),
.locked(),
.clk_in1(CLK100MHZ));

3) I set the JTAG speed to 150 Khz which is the suggested less than half of the clock rate I was trying.

4) I tried having Setup Debug in Synthesis manage my interactions with the ILA and it had the same problem.

The only thing that works for me is to use the 100 Mhz clock. This has the major downside of only capturing a tiny amount of actual data (256 clock periods for a 400 Khz i2c clock using a 64K window) so I'm wasting most of the RAM I have available doing ridiculous oversampling.

I can get the ILA to work, so I don't think the problem is operator error. What am I missing? Anything else I can try?

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14 Replies
Moderator
Moderator
6,166 Views
Registered: ‎04-18-2011

Re: Vivado Debug Core not found ... tried suggestions here already

The JTAG clock should be slower than the clock running the dbg_hub. What is the clock on the debug hub?
Another check is if the design meets timing. This can lead to poor communication with the cores.
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Xilinx Employee
Xilinx Employee
6,103 Views
Registered: ‎08-01-2008

Re: Vivado Debug Core not found ... tried suggestions here already

The clock net connected to dbg_hub is automatically selected by the tool based on the debug core configuration and connections.

However, you can change this clock net by modifying the "connect_debug_port" command in XDC.

The following are possible causes and solutions:

1. The clock that is connected to dbg_hub is a non-free-running clock.

To check which clock net is connected to the dbg_hub, follow these steps in the Vivado GUI:
Open the Synthesized design or Implemented design -> Right click the dbg_hub core in the netlist hierarchy and select "Schematic" -> Double click the "clk" pin
If this clock is a non-free-running clock, change it to a free running one by modifying this command in XDC:

connect_debug_port dbg_hub/clk [get_nets <clock_net_name>]
2. The clock is a free running clock but the signal integrity of this clock net is not good.

Check if the quality of this clock signal on the board is good or not. One example of this issue is if the daughter card connector is not inserted tightly (clock is coming from the daughter card).

3. Try the second solution mentioned in the warning message which is to use the other User Scan Chain number.

For example, the following are the steps to change to use Scan Chain number 2:

Change the C_USER_SCAN_CHAIN property of the dbg_hub core to 2. Please refer to (UG908) for how to change this property.
Manually launch hw_server in the Windows command prompt or a terminal on Linux:

hw_server -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN 2>
Thanks and Regards
Balkrishan
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Observer inflector
Observer
6,065 Views
Registered: ‎08-29-2017

Re: Vivado Debug Core not found ... tried suggestions here already

>The JTAG clock should be slower than the clock running the dbg_hub

Did you actually ready my first post? I said:

    3) I set the JTAG speed to 150 Khz which is the suggested less than half of the clock rate I was trying.

There were no timing problems. This is a very small and simple design at this point.

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Observer inflector
Observer
6,055 Views
Registered: ‎08-29-2017

Re: Vivado Debug Core not found ... tried suggestions here already

@balkris The suggesion in the warning didn't say to try another User Scan Chain number. It said to check it to make sure it was the same number. I checked and they are both 1.

Since your suggestion was different, I tried it. Using the preference tab, I changed it to 0002 and it just gave a red-background error box with this text in it: "bitset::_M_copy_from_ptr"

 

The same command from the TCL command line gives the same error on the following line like:

set_property BSCAN_SWITCH_USER_MASK 0002 [get_hw_devices xc7a35t_0]
bitset::_M_copy_from_ptr

I can reproduce this issue 100% of the time.

Like I said in the subject, I TRIED ALL THE SUGGESTIONS HERE ALREADY. Which ,eans, since I don't want to waste my time or yours, I actually tried to find prior problems with missing debug cores. So I already read the suggestions you've offered above.

Look, I know you get a bunch of junior programmers, college students who don't know how to debug, etc. I'm not one of them.

This is a real bug and all the suggestions offered DO NOT WORK.

Do any of you have an Artix Arty board? If so, I'll send you a sample project so you can reproduce.



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Observer inflector
Observer
6,053 Views
Registered: ‎08-29-2017

Re: Vivado Debug Core not found ... tried suggestions here already

I tried a 125000 JTAG connection, that's slower than both 400KHz and 8MHz which are the clocks I mentioned trying in my first post.

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Observer inflector
Observer
6,052 Views
Registered: ‎08-29-2017

Re: Vivado Debug Core not found ... tried suggestions here already

> 1. The clock that is connected to dbg_hub is a non-free-running clock.

 

The clock wizard generated 8Mhz clock is free running, so is my other clock I tested both.

connect_debug_port dbg_hub/clk [get_nets <clock_net_name>]

2. The clock is a free running clock but the signal integrity of this clock net is not good.

The Vivado wizard clock should be as good a clock signal as you can get.

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Observer inflector
Observer
6,051 Views
Registered: ‎08-29-2017

Re: Vivado Debug Core not found ... tried suggestions here already

The 100Mhz clock that's coming into the Arty works fine at 100Mhz so any derived clocks that are much slower should also be good signals.

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Observer inflector
Observer
6,046 Views
Registered: ‎08-29-2017

Re: Vivado Debug Core not found ... tried suggestions here already

I have uploaded a setup for another reproducible bug I've reported that includes everything you'd need to get this bug to surface except you'd need to add an ILA core to it and try passing in the same slower clock. The slow clocks also cause problems with a dual-clock FIFO not ever finishing it's reset.

These problems may have the same underlying root cause, especially if the ILA uses a dual-clock FIFO.


See the project uploaded here:

https://forums.xilinx.com/t5/BRAM-FIFO/Dual-Clock-FIFO-Reset-Hangs-for-large-clock-speed-difference/m-p/806573#M3660

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Moderator
Moderator
5,774 Views
Registered: ‎10-19-2011

Re: Vivado Debug Core not found ... tried suggestions here already

Is the clock in reset when the device powers up? Are you sending the clock through any other logic/muxing? some other users suggest this already, but this is almost always a clocking problem.

 

You could also output the clock to pin and scope the frequency to make sure its correct, and available (free running).

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Moderator
Moderator
3,537 Views
Registered: ‎02-09-2017

Re: Vivado Debug Core not found ... tried suggestions here already

Hi @inflector,

 

What version of Vivado and what type of cable are you using? Is it a SmartLynq cable?

 

I just found out about an issue that sometimes SmartLynq doesn't detect ILA in Vivado 2017.3. It also issues the same warning [Labtools 27-3403] that you are seeing.

 

Please let us know if that is the case so we can provide you with a solution.

 

Thanks.

Andre Guerrero

Product Applications Engineer

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Newbie dstocek-m
Newbie
3,529 Views
Registered: ‎01-23-2018

Re: Vivado Debug Core not found ... tried suggestions here already

Hi @anunesgu,

 

Does this issue exist in 2017.4 as well?  I am using 2017.4 with the SmartLynq cable and it is not able to find my ILA core.  If I switch back to the Platform USB cable, it works fine.  Please post or send me a solution if there is one.

 

Thanks

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Moderator
Moderator
3,519 Views
Registered: ‎02-09-2017

Re: Vivado Debug Core not found ... tried suggestions here already

Hi @dstocek-m,

 

It is possible that the issue might happens with 2017.4 as well. The issue has to do with updating the Smarlynq firmware.

 

Could you please try the following and let us know if it worked for you?

 

 How to update the smartlynq cable firmware from 2017.2 to 2017.3 using vivado? 

 

STEP 1: Connect the power and Ethernet cable to the SmartLynq Data Cable module. 

 

  1. Plug the power adapter barrel plug into the DC power jack on the SmartLynq module. 
  2. Plug the Ethernet cable into the SmartLynq module and attach it to your network. 
  3. Attach the appropriate country plug to the power adapter and plug into an open AC outlet. 
  4. The SmartLynq Data Cable powers up and the display shows self-check information. 
  5. The SmartLynq Data Cable acquires and displays an IP address, for example: 

smartlynq_1.jpg

 

STEP 2: Connect the SmartLynq Data Cable to the target board. 

 

  1. Connect the SmartLynq Data Cable module to the JTAG interface on the target board. 
  2. Open the Hardware Manager in the Vivado tool. 
  3. To create a new hardware target, click Open Target and choose Open New Target.
  4. The Open New Hardware Target wizard appears. Click Next. 
  5. In the Connect to list box, pull-down Remote server.
  6. In the Host name field, specify the IP address shown on the SmartLynq module display. Click Next. On the SmartLynq Data Cable module display, VREF ON appears if the target board is powered up and VREF OFF appears if the target board does not have power.

 Note: The target board must be powered on in order to connect with the Vivado Hardware Manager. With the board powered on, you can connect using the Open New Hardware Target wizard.

  

STEP 3: Update the SmartLynq cable firmware from 2017.2 to 2017.3

 

  1. Run the update_hw_firmware command.

smartlynq_2.jpg

 

b. After successfully updating the firmware Vivado HW manager will display the info message: 

smartlynq_3.jpg

 

c. Disconnect from the HW server and power cycle the SmartLynq before reconnecting. The SmartLynq cable display will suggest the updated firmware version. 

smartlynq_4.jpg

 

Andre Guerrero

Product Applications Engineer

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Newbie dstocek-m
Newbie
3,503 Views
Registered: ‎01-23-2018

Re: Vivado Debug Core not found ... tried suggestions here already

Hi @anunesgu,

 

That did the trick.  Thanks!

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Visitor onnerb
Visitor
3,359 Views
Registered: ‎02-22-2018

Re: Vivado Debug Core not found ... tried suggestions here already

I had the same problem (VIO debug core) using the SmartLynq cable (Firmware version 2017.2)  with Vivado 2017.4. 

Updated the SmartLynq firmware to 2017.4 and that fixed the problem.

 

Thanks.

 

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