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Registered: ‎06-08-2017

WARNING: [Labtools 27-3413] Dropping logic core with cellname... at location...

I am getting the following warnings when I try to use the debug probes in my design:

WARNING: [Labtools 27-3413] Dropping logic core with cellname:'u_ila_0' at location 'uuid_23E7D65A79BC59F7BC47406C1714DFAE' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7k160t_0 and the probes file(s) C:/Users/danie/OneDrive/Desktop/servos326MOT_board1_HD/Implement/top/top.ltx.
The device design has 1 ILA core(s) and 0 VIO core(s). 0 ILA core(s) and 0 VIO core(s) are matched in the probes file(s).
1. Reprogram device with the correct programming file and associated probes file(s) OR
2. Goto device properties and associate the correct probes file(s) with the programming file already programmed in the device.

I marked the signals I wasngted to debug in my design with

(* mark_debug = "true" *)

then use the wizard in the synthesis DCP to generate the constraints for the debug probe:

create_debug_core u_ila_0 ila
set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]

set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list clk10]]

set_property port_width 16 [get_debug_ports u_ila_0/probe0]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {s_in_0[0]} {s_in_0[1]} {s_in_0[2]} {s_in_0[3]} {s_in_0[4]} {s_in_0[5]} {s_in_0[6]} {s_in_0[7]} {s_in_0[8]} {s_in_0[9]} {s_in_0[10]} {s_in_0[11]} {s_in_0[12]} {s_in_0[13]} {s_in_0[14]} {s_in_0[15]} ]]

create_debug_port u_ila_0 probe
set_property port_width 16 [get_debug_ports u_ila_0/probe1]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {s_in_1[0]} {s_in_1[1]} {s_in_1[2]} {s_in_1[3]} {s_in_1[4]} {s_in_1[5]} {s_in_1[6]} {s_in_1[7]} {s_in_1[8]} {s_in_1[9]} {s_in_1[10]} {s_in_1[11]} {s_in_1[12]} {s_in_1[13]} {s_in_1[14]} {s_in_1[15]} ]]

I implement the design and write_bitstream, then I use write_debug_probes to write the .ltx file from my routed DCP.

Any idea where this might be going wrong?

The routed DCP says the debug probe is placed and routed.

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2 Replies
Registered: ‎02-09-2017

Re: WARNING: [Labtools 27-3413] Dropping logic core with cellname... at location...

Hi @dschussheim,


This issue, in most cases, happens because the clock for the ILA is not free-running or is not being received by the ILA at all.

Could you let us know where that clock comes from?

How are you inputting that clock into the board?

Do you use any MMCM/PLL?

Does the rest of the logic work? can you maybe try to route this clock to an output pin/LED and see if it's actually working?




Andre Guerrero

Product Applications Engineer

Don’t forget to reply, kudo, and accept as solution.
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Registered: ‎06-08-2017

Re: WARNING: [Labtools 27-3413] Dropping logic core with cellname... at location...

The clock comes from an MMCM. All the other logic works.

It looks like this issue could be related to the Hierarchical Design flow from UG946. I'm using that flow to implement some of the modules in my design OOC.

When I synthesize and implement the project with no OOC modules (like standard project mode flow), the debug works. When I add in an OOC module (even one I'm not debugging) I get the warning, and the debug doesn't work.

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