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Adventurer
Adventurer
886 Views
Registered: ‎11-17-2017

What does free clock mean?

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When I use debug to monitor a signal, after downloading the bit file, vivado prompts me for a free clock.The board I use is zc706.My design has been posted.What's wrong with my design?

微信图片_20180505120105.jpg
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Moderator
Moderator
1,148 Views
Registered: ‎02-09-2017

Re: What does free clock mean?

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Hi @chenyang1994,

 

I can't see very well on the picture you posted, but looks like the clock for the dbg_hub and the ILA is coming from a block called "clock generation". What is that block doing? is it a flip-flop/counter that you are using to lower the clock speed?

What is the original clock speed coming into the board?

 

The concept of free clock is a clock that is non-gated, non-reset dependable, not interrupted, and not derived from user clocks or their sources.

That really means that you would need to either use the clock coming into the board straight from the oscillation, or if you need to lower/increase that clock frequency, you can use a PLL/MMCM. 

 

As a test, you can leave the rest of your logic using the clock as it is now, but change the clock for the dbg_hub and ILA to the board input clock (from oscillator). That should work.

 

Thanks,

Andre Guerrero

Product Applications Engineer

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Moderator
Moderator
1,149 Views
Registered: ‎02-09-2017

Re: What does free clock mean?

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Hi @chenyang1994,

 

I can't see very well on the picture you posted, but looks like the clock for the dbg_hub and the ILA is coming from a block called "clock generation". What is that block doing? is it a flip-flop/counter that you are using to lower the clock speed?

What is the original clock speed coming into the board?

 

The concept of free clock is a clock that is non-gated, non-reset dependable, not interrupted, and not derived from user clocks or their sources.

That really means that you would need to either use the clock coming into the board straight from the oscillation, or if you need to lower/increase that clock frequency, you can use a PLL/MMCM. 

 

As a test, you can leave the rest of your logic using the clock as it is now, but change the clock for the dbg_hub and ILA to the board input clock (from oscillator). That should work.

 

Thanks,

Andre Guerrero

Product Applications Engineer

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Moderator
Moderator
781 Views
Registered: ‎10-19-2011

Re: What does free clock mean?

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In general a clock generator module is going to have a lot of startup and configuration logic - delaying the clock. I am unsure about your design, but it could also have some delayed reset logic. Anunesgu gave a great explanation. The ZC706 has many different free running clocks onboard. Many of the example designs for that board use ILAs. You could load of one of those designs and check out the clock source.

https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html#documentation
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Adventurer
Adventurer
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Registered: ‎11-17-2017

Re: What does free clock mean?

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In addition, I have another question.How do I know if the pin's default level is high or low?When I binding the RESET signal on the pin,it shows that my clock generate is always reset.Thanks.

 

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