11-02-2009 05:34 AM
am using xilinx 10.1 . i want to check the power consumption for my design. i have checked the power consumption for two different
designs,but it shows same power consumption for the two different designs. i dont know how to proceed with this. can anyone suggest
thanks in advance
11-02-2009 09:06 AM
Maybe the power is the same in these two designs?
The main cause of dynamic power is the clock frequency: are the clock frequencies the same? Different?
The static power will not be different, regardless of the design.
IO power can also be the dominant power in a design: how different are the IO's?
What does the spreadsheet power estimator tell you about these two designs?
11-02-2009 09:46 PM
there is no clock input in my design. i have checked the power for the following two different multipliers.
1. Normal 8bit array multiplier.
2. 8bit booth multiplier.
but the xpower analyzer shows same power for the above designs. due to this am unable to proceed.
11-03-2009 07:27 AM
If you have no clock, you have no dymanic power.
All designs will meaasure equal power, and all predictions of power will be identical.
11-03-2009 10:41 PM
thanks for your kind reply.
actually am solving one ieee paper. in that they have mentioned
two different multipliers( normal and booth),and its power consumption. the power consumption,delay,
resources usage of booth is less when compared to array mutiplier.
but for me it shows same power consumption. how can i show the different power by using xpower analyzer .
11-04-2009 07:31 AM
Create a test bench, with data vectors as inputs.
You probably need 10K to 50K input vectors. Use a LFSR to generate your data (perhaps write a c program to generate the vectors).
Use the same vectors on each design.
Set a clock rate to push the vectors into the two different designs (100 MHz, 50 MH whatever they are able to run at -- basically as fast as you constrained the design).
Once you have "real' data, happening at a real interval, then you will get a reasonably accurate result.
11-13-2009 07:39 AM
If you do not have a clock, you will have zero dynamic power.
"If you do nothing, you get nothing"
An analogy: a person is wandering around, under a streetlamp, at night, looking for something. You walk up and ask: "What are you looking for?" He answers, "my keys."
"Where did you lose them," you ask. "I lost them over there" (pointing into the darkness)
"So why are you looking here?" you ask. "Because the light is here!"
Just like the story, you are looking for your' keys' under the 'streetlight', because where your 'keys' really are, are in the darkness. Think about it, you are doing something very wrong.
In other words, you need to supply many (thousands) of random multipliers and multiplicands, clocked continuously into the multilier to see the effect of switching, and the dynamic power.
Dyanmic Power is C*V^2*F: capcitance of wires switched, times voltage squared, times the CLOCK FREQUENCY.
If F=0, .... solve the equation!
Total power is staic + dynamic.
If dynamic =0, ... solve the equation!
The static power is always the same: if you use it, or not, the static component is always still there (those transistors are always in the chip, and always leaking, regardless of what you have programmed the chip to do.
11-19-2009 04:31 AM
i understood the problem. if there is no clock input means the dynamic power will be zero and
resultant power is same.
i already told you that am solving one ieee paper( booth multiplier for low power design), in that they
generated the power difference for normal and booth multiplier.
how it is possible?
11-19-2009 07:26 AM
Supply test vectors in a test bench, and 'clock' them through the design (on each cycle, supply a new set of vectors).
Or, build it, and measure the power directly while operating at 100 MHz, or whatever speed they run at (keeping the speed on both, the same).
06-26-2012 07:24 AM
I have a question about dynamic power. For example we have a circuit which it has 8 flip flops, then we implement it in two ways, in the first we compel the design to implemented in one slice (each slice for example has 8 flip flops) and secondly compel the same circuit to implemented in 8 slice(just one flip flop from each slice used). Are their dynamic power different? By this question I want to say if a circuit has more flip flops but impediment in fewer slices, weather its dynamic power is less than a circuit with lower flip flops but occupy more slices?
06-26-2012 07:28 AM
Packing logic into as few slices as possible yields the lowest dynamic power.
The BUFG H-clock tree has bits to turn off the leaves of the tree to save power at the slice level, so using the fewest number of slices means less dynamic power.
Packing logic close together yields the fastest (shortest ) paths, and hence the lowest dynamic power.
Generally synthesizing, placing and routing for best performance (lowest delay) also yields best dynamic power at the same time. Optimizing for are can sometimes provide a better power result, too: try both.