04-10-2013 06:00 AM
in my design i have two mmcm's in two different v-6 FPGA's..
the clocks coming to the two MMCM are in zero degrees.but the outputs from the two MMCM's are in 90 degrees out of phase..
can u please tell me is there any way to phase align the divided output clocks from different MMCM's
thanks in advance
04-10-2013 10:27 AM
Synchronizing the M and D counters in separate MMCM (DCM), even in the same device is not possible (it is not a feature).
You may try resetting the MMCM until it just happens to align (not very elegant).
Perhaps someone can comment on how to avoid this problem in the first place.
04-11-2013 09:44 PM
thanks for the immediate reply..
(You may try resetting the MMCM until it just happens to align (not very elegant).)
reset i can apply multiple times and check in simulation whether clocks are algined or not.but in testing i may not know whether they are aligned or not with perticular reset.
i wanted to try the following,
in mmcm i am seeing one port called "clk_out1_CLR" by driving same signal to both MMCM.i will first try it in the simulations.