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swapnamala@gmail.com
Participant
Participant
6,345 Views
Registered: ‎07-07-2010

divided output clock from two MMCM's

Hi,

 

in my design i have two mmcm's in two different v-6 FPGA's..

 

the clocks coming to the two MMCM are in zero degrees.but the outputs from the two MMCM's are in 90 degrees out of phase..

 

can u please tell me is there any way to phase align the divided output clocks from different MMCM's

 

thanks in advance

 

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2 Replies
austin
Scholar
Scholar
6,333 Views
Registered: ‎02-27-2008

s,

 

Synchronizing the M and D counters in separate MMCM (DCM), even in the same device is not possible (it is not a feature).

 

You may try resetting the MMCM until it just happens to align (not very elegant).

 

Perhaps someone can comment on how to avoid this problem in the first place.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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swapnamala@gmail.com
Participant
Participant
6,315 Views
Registered: ‎07-07-2010

Hi,

 

thanks for the immediate reply..

 

(You may try resetting the MMCM until it just happens to align (not very elegant).)

reset i can apply multiple times and check in simulation whether clocks are algined or not.but in testing i may not know whether they are aligned or not with perticular reset.

 

i wanted to try the following,

in mmcm i am seeing one port called "clk_out1_CLR" by driving same signal to both MMCM.i will first try it in the simulations.

 

thanks

 

 

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