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Explorer
Explorer
10,112 Views
Registered: ‎02-04-2011

generating VHDL cores for chipscope ILA and CON

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Hi,

      I generated chipscope cores using core generator in ISE14.4. But i find that these are in verilog. When i check the project settings in chipscope i see that only verilog option is present no VHDL. But my design is VHDL so it will be god if i can generate VHDL cores.

 

thanks for the support

waris

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1 Solution

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Moderator
Moderator
17,360 Views
Registered: ‎04-17-2011

Re: generating VHDL cores for chipscope ILA and CON

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Please try the below steps:
1. Select the Top Module of your design in ISE Project Navigator and right click
2. Click on Design Properties
3. Scroll down and look for Preferred Language

4. Set it to VHDL

 

Design_Prop.PNG

Regards,
Debraj
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4 Replies
Scholar pratham
Scholar
10,108 Views
Registered: ‎06-05-2013

Re: generating VHDL cores for chipscope ILA and CON

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HI,

 

Do check your design properties and check prefered language it should be VHDL if you want to  generate chipscope core in VHDL.

 


Regards,

Prathamesh

 

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-Pratham

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Explorer
Explorer
10,101 Views
Registered: ‎02-04-2011

Re: generating VHDL cores for chipscope ILA and CON

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I confirmed in the project settings of core generator. There is no option of VHDL . Only verilog?
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Moderator
Moderator
17,361 Views
Registered: ‎04-17-2011

Re: generating VHDL cores for chipscope ILA and CON

Jump to solution

Please try the below steps:
1. Select the Top Module of your design in ISE Project Navigator and right click
2. Click on Design Properties
3. Scroll down and look for Preferred Language

4. Set it to VHDL

 

Design_Prop.PNG

Regards,
Debraj
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
Explorer
Explorer
10,084 Views
Registered: ‎02-04-2011

Re: generating VHDL cores for chipscope ILA and CON

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dear debraj.

                       Yes i checked and it was verilog . I have changed it t VHDL. Will try tommorrow to generate in Coregenerator with this setting. 

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