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conanandai100
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Registered: ‎12-01-2010

need a slow clock for ILA

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Hi all,

 

I am trying to use vivado2017.2 with KC705 to run my project. When I use the ILA, the input clock is too fast that I cannot get all the sample I want. The depth of ILA does not help much. I also try the MMCM, but it only offers an output clock which is no slower than 5MHz.

 

Then I refer to this solution:

 

https://forums.xilinx.com/t5/Implementation/Deriving-a-slow-clock/td-p/672341

 

However, when I download the bitstream, I get the following warning:

 

WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.

 

Given the free running clock issue, is it possible to find a way to generate a valid slow clock for ILA? Like 1KHz or even slower.

 

Thanks in advance.

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gszakacs
Professor
Professor
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Registered: ‎08-14-2007

In Vivado, I believe the new term for storage qualification is "Capture Control."  This setting needs to be turned on in the trigger options when you create the ILA.  Then it's possible in the debugger to only capture when some trigger condition is active.  If this needs to be a complex logic function, it may be easiest to create that in hardware and then just include the signal in your trigger word.  That's what I meant by a clock enable.  For example if you wanted to sample at a rate of 1 KHz, you would create a counter that divides your 200 MHz clock by 200,000 and include the carry-out from that counter in your trigger word.  If your data comes in at random intervals, but you have a data enable signal that indicates which cycles have new valid data, then include that in your trigger word and use it as the capture (storage) qualifier.  In any case you're looking for a signal that indicates which clock cycles you want to capture data on.

-- Gabor

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gszakacs
Professor
Professor
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Registered: ‎08-14-2007

I think you're going about this the wrong way.  The ILA clock must be at least twice the frequency of the JTAG clock in order to avoid the error you're getting.  Instead of trying to slow down the clock to the ILA, you should create a slow clock enable signal and use that as a storage qualifier.  Then the ILA is clocked at the original speed of your logic, but you only capture data on cycles where the clock enable is active.

-- Gabor
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conanandai100
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Registered: ‎12-01-2010

Hi Gabor,

 

Thank you for the quick reply.

 

I am new for using ILA. Just a little bit confused with the slow clock enable signal you mentioned in your reply. Given a ILA input clock of 200MHz, what is the slow clock enable signal used for? I assume that there is no enable input in ILA IP, is that correct? I tried the capture control and there was no change on the input side.

 

ila.png

 

I also check the user guide:

 

https://www.xilinx.com/support/documentation/ip_documentation/ila/v6_2/pg172-ila.pdf

 

There seems to be an update on Storage Qualifier, but no details are provided.

 

Then if the enable signal means my own logic, the problem is that my logic generate output in an asynchronous way, so it can take lots of memories to store enough samples. Surely I may use MIG to store the captured data in SDRAM and transfer the data with UART, it does not seem to be as clear as using the ILA.

 

not converge.png

 

So could you please explain a little bit about how to use the slow clock enable if I did not get your point?

 

Thanks

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gszakacs
Professor
Professor
9,374 Views
Registered: ‎08-14-2007

In Vivado, I believe the new term for storage qualification is "Capture Control."  This setting needs to be turned on in the trigger options when you create the ILA.  Then it's possible in the debugger to only capture when some trigger condition is active.  If this needs to be a complex logic function, it may be easiest to create that in hardware and then just include the signal in your trigger word.  That's what I meant by a clock enable.  For example if you wanted to sample at a rate of 1 KHz, you would create a counter that divides your 200 MHz clock by 200,000 and include the carry-out from that counter in your trigger word.  If your data comes in at random intervals, but you have a data enable signal that indicates which cycles have new valid data, then include that in your trigger word and use it as the capture (storage) qualifier.  In any case you're looking for a signal that indicates which clock cycles you want to capture data on.

-- Gabor

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conanandai100
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Registered: ‎12-01-2010

That is exactly what I am looking for. I will try it then.

 

Thanks for your great help!

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