10-22-2015 03:49 AM
everyone! i used jtag download bit files to fpga. some bits file can work. some download fails. i don't know
ERROR: [Labtools 27-3165] End of startup status: LOW
program_hw_devices: Time (s): cpu = 00:00:27 ; elapsed = 00:00:25 . Memory (MB): peak = 758.047 ; gain = 0.000
ERROR: [Common 17-39] 'program_hw_devices' failed due to earlier errors.
i dump the register in the two situation。table.xlsx is failed.
somebody help !
10-23-2015 02:50 AM
Direct RSA bitstream configuration via JTAG is not supported in the 2015.3 version of Vivado Device Programmer.
Please check the following answer record.
10-29-2015 04:21 AM
11-05-2015 07:47 PM
Did that help?
11-05-2015 10:23 PM
sorry, after we changed source code,new implemented bits file can work, so i had not fouse on the problem。
Are you using the same board to dump all bit files?
Yes,we dumped the two files in the same board.
Can you please tell us what setting you are changing while generating two bit files i.e. failing and passing?
we did not change any settings, but just changed verilog source code.
the project didn't saved. you konw after the bit file didn't not work, we changed source code implemented again，new bits can work.
01-04-2016 10:20 PM