hi,
Now you have to write state machine code in verilog/vhdl by selecting either verilog new source/vhdl new source.
you can check the standard language template for types of fsm coding.
thanks
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For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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Don’t forget to reply, kudo, and accept as solution.
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