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Registered: ‎08-31-2017

Access the same variable by different mode path in HLS ?

Hi, dear elites,

I'm working on a case with the following spec in HLS. Provided that there is an internal vector array which supports initialization mode and computing mode. Firstly, user will configure to program the initial value of the array via AXI lite bus and then kick off the block to run. Once it gets started to execute, the value of vector array will be updated by internal computation unit which user cannot program via AXI lite bus. If the case is the flow guaranteed, how do you suggest in the coding style of the HLS code? I don't know if there has anything I should take into account while implementation in HLS.




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Scholar u4223374
Registered: ‎04-26-2015

Re: Access the same variable by different mode path in HLS ?

The only things you really need to be careful of with AXI Lite are RAM requirements and performance.

RAM requirements

AXI Lite is 32-bit. HLS will pack multiple elements into a single AXI Lite element (eg. two 15-bit values in one 32-bit memory element). However, if you use 18-bit values (for example) then it can't apply this packing - you can't fit two 18-bit values into a single 32-bit one. Instead it'll create a 32-bit RAM, leaving the upper 14 bits of each element empty. If you were expecting an 18-bit RAM (because the Xilinx chips can support that mode very nicely) then you're going to find that it uses twice as much RAM as you had planned.



With an array accessible on AXI Lite, one RAM port is permanently attached to the AXI Lite interface. The other port is available for HLS to use. An array declared inside the HLS block with no outside accessibility will have both ports available for HLS to use, so in certain situations you can get twice the throughput.


In both cases, a solution is to use something other than AXI Lite on the interface (eg. an AXI Stream) and use that to populate an internal array. For performance you can have an AXI Lite array on the interface and copy that to one or more internal arrays (for high performance you may use a heavily partitioned internal array). Or you can just design the block so that neither of these is actually a concern.


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