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Explorer
Explorer
11,422 Views
Registered: ‎11-21-2014

Difference among Interface, Resource, Stream directives for Interface Synthesis

Hi,

 

I am currently learning HLS. I have troubles understanding differences between directive options like Interface, Resource and Stream. They looked same to me as I need to use AXI4Stream. Furthermore, selecting one of the options I do get more sub options like variable required, off, depth as optional. I could not understand them neither. Xilinx documentation seem to be poor in those explanation. Kindly somebody please help to understand those terms.

 

Thanks

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6 Replies
Moderator
Moderator
11,380 Views
Registered: ‎04-17-2011

Re: Difference among Interface, Resource, Stream directives for Interface Synthesis

The directives are simplified in the latest version of tools where you can use the directive axis for defining AXI4 stream. Interface is to let the tool know what kind of Interface is needed at the IP boundary. Resource is used to highlight the kind of adapter needed for implementing that Interface.

#pragma HLS INTERFACE axis port=A
Regards,
Debraj
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Explorer
Explorer
11,375 Views
Registered: ‎11-21-2014

Re: Difference among Interface, Resource, Stream directives for Interface Synthesis

@debrajr .Thanks Debraj for the answer. So, it is necessary or good idea to have both interface and then resource directive to the ports?

Besides, could you provide some resource/links to understand the sub options for those directives?

And another question, how to limit HLS compiler to only generate select signals like ACLK, ACLKEN, ARESTEN, TVALID, TREADY, TDATA, TUSER and TLAST? As I am creating Video IP, I need to remove signals like TID, TDEST, TKEEP and TSTRB.

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Moderator
Moderator
11,295 Views
Registered: ‎04-17-2011

Re: Difference among Interface, Resource, Stream directives for Interface Synthesis

It was needed for the older directives. The latest directives can be used directly. UG902 is the one stop shop for all this information.

Your next question is also mentioned in UG902 (page 177 of 2014.4 version)
#include "ap_axi_sdata.h"
void example(ap_axis<32,2,5,6> A[50], ap_axis<32,2,5,6> B[50]){
//Map ports to Vivado HLS interfaces
#pragma HLS INTERFACE axis port=A
#pragma HLS INTERFACE axis port=B
int i;
for(i = 0; i < 50; i++){
B[i].data = A[i].data.to_int() + 5;
B[i].keep = A[i].keep;
B[i].strb = A[i].strb;
B[i].user = A[i].user;
B[i].last = A[i].last;
B[i].id = A[i].id;
B[i].dest = A[i].dest;
}
}
Regards,
Debraj
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Explorer
Explorer
11,290 Views
Registered: ‎11-21-2014

Re: Difference among Interface, Resource, Stream directives for Interface Synthesis

@debrajr . Thanks Debraj. I do have checked this page. My question is "can we chose only select ports of all ports in the struct? Because I can't see any way to synthesize only select ports. The documentation in the same page also says all the ports in structs are synthesized.

 

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Moderator
Moderator
11,259 Views
Registered: ‎04-17-2011

Re: Difference among Interface, Resource, Stream directives for Interface Synthesis

Yes you can select ports from the struct and not use all the stream ports.
Regards,
Debraj
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Explorer
Explorer
10,879 Views
Registered: ‎11-21-2014

Re: Difference among Interface, Resource, Stream directives for Interface Synthesis

@debrajr . Hi Debraj. According to you, I modifyied ap_axi_sdata.h. i.e.

template<int D,int U,int TI,int TD>
  struct ap_axiu{
    ap_uint<D>   data;
  //  ap_uint<D/8> keep;
  //  ap_uint<D/8> strb;
    ap_uint<U>   user;
    ap_uint<1>   last;
  //  ap_uint<TI>  id;
  //  ap_uint<TD>  dest;
  };
As you can see I commented those signals I dont need, but on synthesis I get following errors.

In file included from C:/Xilinx/Vivado_HLS/2014.4/include\hls_video.h:59:
C:/Xilinx/Vivado_HLS/2014.4/include/hls/hls_video_io.h:145:17: error: no member named 'keep' in 'ap_axiu<24, 1, 1, 1>'
            axi.keep = -1;
            ~~~ ^
mod_cfa_interpolation/top.cpp:398:5: note: in instantiation of function template specialization 'hls::Mat2AXIvideo<24, 1080, 1920, 32>' requested here
    hls::Mat2AXIvideo(img_1, dst_axi);

 

 I would like to make IP like color filter array interpolation IP.

ad.png

Please help me to make such IP block's interface.

Thanks in advance.

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