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Observer jirhus
Observer
9,013 Views
Registered: ‎06-19-2013

Estimated clock are greater than target

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Hello,

I'm new in Vivado HLS and a want to design easy filter for image processing. The HLS component is connected throught AxiStream IN and AxiStreamOUT.

When I run Synthesis without pipelining (the result is in first picture) the estimated clock is  3.68 ns, but interval is 3 clocks. I need result every clock -> II=1 in pipeline. Unfortunately with pipeline directive the estimation clock are greater then target (Picture 2). Is possible design that in interval 1 clock with greater latency and resources?

no_pipeline.PNG
pipeline.PNG
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Observer jirhus
Observer
15,914 Views
Registered: ‎06-19-2013

Re: Estimated clock are greater than target

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I have solved my problem.

The problem was in multiple writing values into EOL a SOL counters and there was problem with pipelining in target clock.

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Xilinx Employee
Xilinx Employee
8,994 Views
Registered: ‎08-17-2011

Re: Estimated clock are greater than target

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that's strange because it met timing in the non-pipelined version; can you post your design and directives used?
- Hervé

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Observer jirhus
Observer
8,991 Views
Registered: ‎06-19-2013

Re: Estimated clock are greater than target

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There is my design:

 

#include "ap_int.h"
#include "ap_shift_reg.h"

#define FRAME_WIDTH 20
#define FRAME_HEIGHT 10

#define MASK_WIDTH 3
#define BUFFER_DEPTH 2 * FRAME_WIDTH + MASK_WIDTH

typedef struct {
	ap_uint<10> data;
	ap_uint<1> user;
	ap_uint<1> last;
} MyAxiStream;

void sobel(MyAxiStream *Image_IN, MyAxiStream *Image_OUT){
	#pragma HLS PIPELINE II=1
	#pragma HLS INTERFACE axis port=Image_IN
	#pragma HLS INTERFACE axis port=Image_OUT

	static ap_shift_reg<ap_uint<10>, FRAME_WIDTH-MASK_WIDTH> buffer1;
	static ap_shift_reg<ap_uint<10>, FRAME_WIDTH-MASK_WIDTH> buffer2;
	static ap_uint<10> a,b,c,d,e,f,g,h,i;
	static ap_uint<12> SOFcounter = 0;
	static ap_uint<12> EOLcounter = 0;
	static ap_uint<1> valid = 0;
	ap_uint<10> result = 0;
	ap_uint<1> last = 0;
	ap_uint<1> user = 0;



	//read and shift:
	i = h;
	h = g;
	g = buffer1.shift(f, FRAME_WIDTH-MASK_WIDTH-1, true);
	f = e;
	e = d;
	d = buffer2.shift(c, FRAME_WIDTH-MASK_WIDTH-1, true);
	c = b;
	b = a;
	a = Image_IN->data.to_int();
	last = Image_IN->last.to_int();
	user = Image_IN->user.to_int();


	//pixel counter
	SOFcounter++;
	EOLcounter++;
	if(user == 1){
		SOFcounter = 1;
		EOLcounter = 1;
	}


	//apply mask
	result += 2 * i;
	result += 1 * h;
	//result.data += 0 * g;

	result += 1 * f;
	//result.data += 0 * e;
	result += -1 * d;

	//result.data += 0 * c;
	result += -1 * b;
	result += -2 * a;


	//set outputs - start of frame
	if(SOFcounter ==  2*FRAME_WIDTH+MASK_WIDTH){
		user = 1;
		valid = 1;

	}

	//set outputs - end of line
	if(EOLcounter == FRAME_WIDTH){
		last = 1;
		EOLcounter = 0;
	}


	if(valid == 1){
		Image_OUT->data = result;
		Image_OUT->user = user;
		Image_OUT->last = last;
	}


}

 

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Observer jirhus
Observer
15,915 Views
Registered: ‎06-19-2013

Re: Estimated clock are greater than target

Jump to solution

I have solved my problem.

The problem was in multiple writing values into EOL a SOL counters and there was problem with pipelining in target clock.

0 Kudos