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Scholar pedro_uno
Scholar
6,713 Views
Registered: ‎02-12-2013

Extra BRAM port

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I have an HLS block that has this function definition.

 

bool mat_inv_4x4(float m[16], float inv[16])


I expect to get one BRAM port for my input matrix "m" and one BRAM port for my result matrix "inv".  Unfortunately, HLS creates code that has two ports into the input BRAM.  Below is the entity statement of the HLS synthesized code.  I tried to highlight the relevant ports. If HLS is using both ports into the "m" BRAM block how can I load the input data?

 

entity mat_inv_4x4 is

port (

ap_clk : IN STD_LOGIC;

ap_rst : IN STD_LOGIC;

ap_start : IN STD_LOGIC;

ap_done : OUT STD_LOGIC;

ap_idle : OUT STD_LOGIC;

ap_ready : OUT STD_LOGIC;

m_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);

m_ce0 : OUT STD_LOGIC;

m_q0 : IN STD_LOGIC_VECTOR (31 downto 0);

m_address1 : OUT STD_LOGIC_VECTOR (3 downto 0);

m_ce1 : OUT STD_LOGIC;

m_q1 : IN STD_LOGIC_VECTOR (31 downto 0);

inv_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);

inv_ce0 : OUT STD_LOGIC;

inv_we0 : OUT STD_LOGIC;

inv_d0 : OUT STD_LOGIC_VECTOR (31 downto 0);

inv_q0 : IN STD_LOGIC_VECTOR (31 downto 0);

ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) );

end;

 

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DSP in hardware and software
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1 Solution

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Xilinx Employee
Xilinx Employee
9,972 Views
Registered: ‎08-17-2011

Re: Extra BRAM port

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Hello Pete,

 

I guess that the tool was too optimitic, and tried to use too many ports.

 

Please use this pragma or equivalent directive
#pragma HLS RESOURCE variable=m core=RAM_1P_BRAM

 


What comes below is just random thoughts - I may even be wrong ;-)
 

So, as a side comment, since I recognize your code, the inv port above is read and write since your code is also using inv as temporary storage.

 

pseudo-code you had:

 

part1: for (pos = 0; pos < 16; pos++)
   inv[pos] = expression_for_sum_of_products_of(m,pos)

 

for (i = 0; i < 16; i++)
   inv[i] = inv[i] * det;

 

*If* array "inv" from the part1 is made as a new internal temporary array, then your top level "inv" port will be write-only -- at this point the tool may also decide to use 2 ports, I'm not sure here what are the rules (it seems to be greedy rules).


This may reduce (=improve) the latency at the expense of storage - I let you check but the numbers are small that anything can balance the results one way or another (talking about latency / resources).


The next step may be to actually write back the data into m, effectively inversing "in place" the 4x4 matrix - this may or may not be what you want and just depends what you're looking for.

 

 

Have fun investigating :)

 

- Hervé

SIGNATURE:
* New Dedicated Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.
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2 Replies
Xilinx Employee
Xilinx Employee
9,973 Views
Registered: ‎08-17-2011

Re: Extra BRAM port

Jump to solution

Hello Pete,

 

I guess that the tool was too optimitic, and tried to use too many ports.

 

Please use this pragma or equivalent directive
#pragma HLS RESOURCE variable=m core=RAM_1P_BRAM

 


What comes below is just random thoughts - I may even be wrong ;-)
 

So, as a side comment, since I recognize your code, the inv port above is read and write since your code is also using inv as temporary storage.

 

pseudo-code you had:

 

part1: for (pos = 0; pos < 16; pos++)
   inv[pos] = expression_for_sum_of_products_of(m,pos)

 

for (i = 0; i < 16; i++)
   inv[i] = inv[i] * det;

 

*If* array "inv" from the part1 is made as a new internal temporary array, then your top level "inv" port will be write-only -- at this point the tool may also decide to use 2 ports, I'm not sure here what are the rules (it seems to be greedy rules).


This may reduce (=improve) the latency at the expense of storage - I let you check but the numbers are small that anything can balance the results one way or another (talking about latency / resources).


The next step may be to actually write back the data into m, effectively inversing "in place" the 4x4 matrix - this may or may not be what you want and just depends what you're looking for.

 

 

Have fun investigating :)

 

- Hervé

SIGNATURE:
* New Dedicated Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Scholar pedro_uno
Scholar
6,692 Views
Registered: ‎02-12-2013

Re: Extra BRAM port

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Hervé,

 

Your advice is good.  The pragma you suggested forced the "m" input array to use only a single BRAM port.  That is what I wanted. The cost was only a very slight increase in latency from 4200 to 4300 clocks.  That is a very good trade off in order to save a BRAM.

 

I ran a VHDL simulation of the block.  The "m" BRAM is not being access so I am not suprised that the latency increase is small.

 

Thanks for the  help.

 

  Pete

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DSP in hardware and software
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