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Visitor thomashkim
Visitor
4,689 Views
Registered: ‎08-02-2012

HLS ap_memory interface question

Hi all,

 

I synthesized my module shown below using HLS

void my_func(float x_r[16384], float x_i[16384], long n, int isign)

 

and HLS synthesized it to have memory interface, which makes sense because memory interface is the default when input and output are passed as array into and out of a function. However, what I don't understand is that it generated "two" inputs for the function. The port description looks as:

 

port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
x_r_address0 : OUT STD_LOGIC_VECTOR (13 downto 0);
x_r_ce0 : OUT STD_LOGIC;
x_r_we0 : OUT STD_LOGIC;
x_r_d0 : OUT STD_LOGIC_VECTOR (31 downto 0);
x_r_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
x_r_address1 : OUT STD_LOGIC_VECTOR (13 downto 0);
x_r_ce1 : OUT STD_LOGIC;
x_r_q1 : IN STD_LOGIC_VECTOR (31 downto 0);
x_i_address0 : OUT STD_LOGIC_VECTOR (13 downto 0);
x_i_ce0 : OUT STD_LOGIC;
x_i_we0 : OUT STD_LOGIC;
x_i_d0 : OUT STD_LOGIC_VECTOR (31 downto 0);
x_i_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
x_i_address1 : OUT STD_LOGIC_VECTOR (13 downto 0);
x_i_ce1 : OUT STD_LOGIC;
x_i_q1 : IN STD_LOGIC_VECTOR (31 downto 0);
n : IN STD_LOGIC_VECTOR (31 downto 0);
isign : IN STD_LOGIC_VECTOR (31 downto 0) );

 

 

As you see above, there are x_r_q0 and x_r_q1 for x_r input, and similar two for x_i input. 

Does anyone know why the tool generates two input ports? 

Thanks,

 

Thomas

 

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4 Replies
Observer h4cks4w
Observer
4,282 Views
Registered: ‎08-16-2013

Re: HLS ap_memory interface question

It would seem that HLS has discovered that it can simultaneously read two independent values from both x_r and x_i.  You'll need to hook up a dual-port block RAM.

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Observer h4cks4w
Observer
4,279 Views
Registered: ‎08-16-2013

Re: HLS ap_memory interface question

Also, I just discovered if you don't want to use a dual-port block RAM you can do something like this:

#pragma HLS RESOURCE variable=x_r core=RAM_1P_BRAM

#pragma HLS RESOURCE variable=x_i core=RAM_1P_BRAM

 

This will get rid of your second read port on each memory interface, probably at the cost of some extra latency.

Moderator
Moderator
4,277 Views
Registered: ‎04-17-2011

Re: HLS ap_memory interface question

Additionally refer to the HLS Synth Report and it gives you more idea on what interface type was synthesized and what resources were used.
Regards,
Debraj
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Scholar pedro_uno
Scholar
4,249 Views
Registered: ‎02-12-2013

Re: HLS ap_memory interface question

Hello,

 

I have found the same behavior in my work.  If HLS can shave any latency by adding an extra port into the memory it will.  This is usually not what you want.  In my case, the extra port only saved about 1% in latency. I used the suggested directives to get rid of the extra port.

 

  Pete

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DSP in hardware and software
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