UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer zasxcd
Observer
2,229 Views
Registered: ‎05-28-2017

Interpreting synthesis report

Can anyone shed some light on how to interpret the synthesis report generated by HLS, latency in particular. Is it reliable? I want to improve timing performance of my PL that I have designed in HLS. After implementing on hardware, I'm measuring the time taken by it via AXI Timer. I tried adding up all the loop latency deescribed in the synthesis report to estimate the time taken but it's not matching (not even near) with the time measured. 

Is there any way to estimate how much time will be taken by the PL in HLS itself, without implementing on hardware everytime I make any changes to see if the performance has improved or not?

Also, any material on how to increase the performance using optimization directives in HLS?

 

Thanks in Anticipation. 

0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
2,220 Views
Registered: ‎08-01-2008

Re: Interpreting synthesis report

you can look into quick Video

https://www.xilinx.com/video/hardware/verifying-your-vivado-hls-design.html

check this ARs as well
https://www.xilinx.com/support/answers/60925.html
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
Scholar u4223374
Scholar
2,220 Views
Registered: ‎04-26-2015

Re: Interpreting synthesis report

Generally the synthesis report is accurate with regards to latency, assuming that everything is ideal. If you have AXI Stream interfaces, HLS assumes that those are never blocked for input or output. For AXI Masters, I think HLS just assumes single-cycle reads/writes - depending on the access done (and bus congestion) this can be anywhere from "very nearly correct" to "totally wrong".

 

The synthesis report also assumes, of course, that specified loop tripcounts are correct. If you've specified that a loop only runs a maximum of five times, but the test data that you're feeding in cases that loop to run a million times, the timing estimate will obviously be wrong.

 

UG902 is the main source of information on optimization directives. If you have a specific case where optimization is needed, post it here and someone might have some ideas.