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Explorer
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Registered: ‎02-08-2018

One HLS block writes image data to RAM while another one reads it. How best to do this?

I have two Vivado HLS blocks in my Xilinx Vivado block design.  One of them inputs an AXI STREAM of image data, and then writes the image data to RAM.  The other Vivado HLS blocks reads that same image data from RAM and uses it as input.  This second block executes over 1000 times for each image frame, and each time, it needs to have access to the original image data.  Therefore, it is important for me to give this block access to the image data every time it executes without having to reread the image data from an AXI STREAM.

I am working with a Virtex 7 FPGA and Microblaze.  So far, I tried making an ap_memory port for the image data array.  This array is output for the EdgeDetector block and input for the QuadDetector block.  Now, however, I am having trouble figuring out how to properly connect these ports in the Vivado block diagram, especially for the QuadDetector block.

temp.pngFirst block (top) and second block (bottom)

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