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Reading HLS IP core AXI-Lite interface registers from XSDB

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Posts: 3
Registered: ‎07-24-2015

Reading HLS IP core AXI-Lite interface registers from XSDB

Hello everyone,

 

I generated an IP core in HLS (from the AXI-Lite interface example) which works with SDK software but I cannot access it's AXI-Lite registers through the XSDB application. I can write normally but not read the values back. The code is the one below.

 

 

#include <stdio.h>

void example(char *a, char *b, char *c)
{
#pragma HLS INTERFACE s_axilite port=a bundle=BUS_A
#pragma HLS INTERFACE s_axilite port=b bundle=BUS_A
#pragma HLS INTERFACE s_axilite port=c register bundle=BUS_A
#pragma HLS INTERFACE s_axilite port=return bundle=BUS_A

*c += *a + *b;
}

 

The registers generated from the synthesis are the ones below:

registers.png

I then used "Export RTL" command to send it to Vivado. I imported it to the project and then I after I generated the bitstream, run SDK and programmed the board and run a hello world application. Then I opened XSDB and tried to access the offsets of the addresses without success. (I also had a GPIO linked to LEDs which worked both in read/write directions)

 

failed_access.png

failed_read_2.png

 

I can write to those addresses without any problem with XSDB but not read them, even though the header file says that those addresses are read/write.

 

Is it possible to read the values from XSDB? Or HLS allows read access only through the SDK suite to those registers?

 

Finally, I use the VCU108 board for the experiments.

 

Regards,

Spyros