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Transfer the HLS generated Verilog-HDL to Altera's FPGA

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Newbie
Posts: 2
Registered: ‎01-17-2016
Accepted Solution

Transfer the HLS generated Verilog-HDL to Altera's FPGA

Hi all,

 

I'm Hiroki Nakahara working at Ehime University, Japan.

 

Today, I tried to generate the HDL codes from the Vivado HLS.
The target device is the Artix7 which is used in the Nexys4 DDR board.
I wrote the C-code which converts the RGB color data into the HSV color ones.
Next, I used the Vivado HLS to generate the Verilog HDLs.

Then, I transfer them to the Altera's Quartus II version 14.0 sp1.

 

Believe it or not, the Quartus II successfully synthesized the HSV converter without no-warnings.
After that, I configured the MAX10 FPGA, and the board runs without any troubles!

 

My question is "Is it possible to use the Vivado HLS in order to a front-end of the Quartus II?".
I'm afraid that this transfer becomes a violation of the Xilinx's Vivado HLS license terms.

 

Regards,
Hiroki


Accepted Solutions
Moderator
Posts: 5,500
Registered: ‎08-01-2008

Re: Transfer the HLS generated Verilog-HDL to Altera's FPGA

you can read the agreement
http://www.xilinx.com/support/documentation/sw_manuals/end-user-license-agreement.txt
Thanks and Regards
Balkrishan
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Moderator
Posts: 5,500
Registered: ‎08-01-2008

Re: Transfer the HLS generated Verilog-HDL to Altera's FPGA

Xilinx Recommend to use Xilinx Device for HLS flow . We have not tested such flow at our end.
So not sure if you may stuck at any point the future.

I think 1-2 design may not enough to valid such flow

I would recommend not use such flow with critical application design
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
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Newbie
Posts: 2
Registered: ‎01-17-2016

Re: Transfer the HLS generated Verilog-HDL to Altera's FPGA

Thank you very much for your kindless reply.

 

How do you think a violation of the Xilinx's Vivado HLS license terms about this topic?

 

Bests,

Hiroki

 

 

Moderator
Posts: 5,500
Registered: ‎08-01-2008

Re: Transfer the HLS generated Verilog-HDL to Altera's FPGA

you can read the agreement
http://www.xilinx.com/support/documentation/sw_manuals/end-user-license-agreement.txt
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
Explorer
Posts: 185
Registered: ‎11-17-2015

回复: Transfer the HLS generated Verilog-HDL to Altera's FPGA

Tools are getting smarter.
Array to RAM conversion may work in both X and Altera tools.

I am not sure how it goes when clock synthesizers and DCMs are involved.
Xilinx Employee
Xilinx Employee
Posts: 3,116
Registered: ‎11-28-2007

Re: Transfer the HLS generated Verilog-HDL to other FPGA's

[ Edited ]

Use of Xilinx software on non-Xilinx devices is clearly prohibited in the end user license agreent (the relevant clause is copied below):

 

4.    Restrictions.
     
    (a)    Special Use Restrictions.  No right is granted hereunder to use the Software or any Bitstream generated by use of the Software to program or develop designs for non-Xilinx Devices;

 

http://www.xilinx.com/support/documentation/sw_manuals/end-user-license-agreement.txt

 


oboe7man wrote:

Thank you very much for your kindless reply.

 

How do you think a violation of the Xilinx's Vivado HLS license terms about this topic?

 

Bests,

Hiroki

 

 


 

Cheers,
Jim
Moderator
Posts: 8,793
Registered: ‎02-27-2008

Re: Transfer the HLS generated Verilog-HDL to other FPGA

"No right is granted hereunder to use the Software or any Bitstream generated by use of the Software to program or develop designs for non-Xilinx Devices"

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose