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Visitor yankh1996
Visitor
380 Views
Registered: ‎03-28-2019

UG871 lab1 error: unable to open output file fir_test.bc, Vivado HLS 2018.2

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I was running UG871 HLS tutorial lab1 and when I was trying to simulate the C code and co-simulate the RTL, I got errors pops up.

I am using Vivado SDx 2018.2 with the hls tools, running under Ubuntu 16.04

The vivado hls logfile shows:

INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
Compiling(apcc) ../../../../fir_test.c in debug mode
INFO: [HLS 200-10] Running '/data/tools/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/apcc'
INFO: [HLS 200-10] For user 'SENSETIME\yankanghong' on host 'szdzcp18030147.domain.sensetime.com' (Linux_x86_64 version 4.4.0-21-generic) on Thu Mar 28 13:50:01 CST 2019
INFO: [HLS 200-10] On os Ubuntu 16.04 LTS
INFO: [HLS 200-10] In directory '/data/HLS_projects/ug871-design-files/Introduction/lab1/fir_prj/solution1/csim/build'
error: unable to open output file '/tmp/apcc_db_SENSETIMEyankanghong/130841553752201081873/fir_test.bc': 'Error opening output file '/tmp/apcc_db_SENSETIMEyankanghong/130841553752201081873/fir_test.bc''
1 error generated.
ERROR: [APCC 202-10] clang compile failed: child process exited abnormally
ERROR: [APCC 202-1] ProcessSources failed
INFO: [APCC 202-3] Tmp directory is /tmp/apcc_db_SENSETIME\yankanghong/130841553752201081873
ERROR: [APCC 202-1] APCC failed.
csim.mk:80: recipe for target 'obj/fir_test.o' failed
make: *** [obj/fir_test.o] Error 1
ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
INFO: [SIM 211-3] *************** CSIM finish ***************
4
while executing
"source /data/HLS_projects/ug871-design-files/Introduction/lab1/fir_prj/solution1/csim.tcl"
invoked from within
"hls::main /data/HLS_projects/ug871-design-files/Introduction/lab1/fir_prj/solution1/csim.tcl"
("uplevel" body line 1)
invoked from within
"uplevel 1 hls::main {*}$args"
(procedure "hls_proc" line 5)
invoked from within
"hls_proc $argv"

Could someone help me with this situation? How could I run the simulation correctly?

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1 Solution

Accepted Solutions
Visitor yankh1996
Visitor
324 Views
Registered: ‎03-28-2019

Re: UG871 lab1 error: unable to open output file fir_test.bc, Vivado HLS 2018.2

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I have solved the problem by creating a new user account without the special character "\". Thanks.

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3 Replies
Moderator
Moderator
344 Views
Registered: ‎06-24-2015

Re: UG871 lab1 error: unable to open output file fir_test.bc, Vivado HLS 2018.2

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@yankh1996 

As given on page 8 of https://china.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug1294-sdsoc-rnil.pdf

Supported OS:

Ubuntu Linux 16.04.3 LTS (64-bit)
- Linux kernel 4.4.0 is supported
- Ubuntu LTS enablement (also called HWE or Hardware Enablement) is not supported

Can you check with some other supported OS?

Thanks,
Nupur
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Visitor yankh1996
Visitor
325 Views
Registered: ‎03-28-2019

Re: UG871 lab1 error: unable to open output file fir_test.bc, Vivado HLS 2018.2

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I have solved the problem by creating a new user account without the special character "\". Thanks.

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Xilinx Employee
Xilinx Employee
292 Views
Registered: ‎09-05-2018

Re: UG871 lab1 error: unable to open output file fir_test.bc, Vivado HLS 2018.2

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Hey @yankh1996,

We're glad you found a solution! Thanks for sharing it your fix and marking it solved, we really appreciate it!

Nicholas Moellers

Xilinx Worldwide Technical Support
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