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Visitor igorft
Visitor
4,940 Views
Registered: ‎11-21-2013

-clock_enable

I've tried to use -clock_enable directive:

 

Vivado HLS creates testbench, that just ties ap_ce pin to 1 - that doesn't make any sense, at least toggle it every clock

 

IS THERE A WAY FOR USER TO CONTROL ap_ce in the testbench???

 

Igor

 

 

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1 Reply
Moderator
Moderator
4,934 Views
Registered: ‎04-17-2011

Re: -clock_enable

The interface configuration setting clock_enable adds global clock enable (CE) to be added
to the RTL design when selected. This adds port ap_ce to the top-level ports: when port
ap_ce is active Low, the clock is inhibited to all registers in the design.
Not sure what you meant by HLS creates testbench as you have to write it manually or write a testbench in RTL once you Export it to Vivado.
Regards,
Debraj
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