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Adventurer
Adventurer
9,087 Views
Registered: ‎09-25-2015

driving a 64bit address bus master with the 32bit address microblaze

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Hi,

 

I have the VC709 Eval Board. This board has two DIM modules 4GB each. With a total amount of 8GB I have a 33-bit address space. The Mig7 has now TWO AXI Slave ports. One per 4GByte DIMM.

 

Those two slave ports are connected to an AXI Mem Interconnect with two Master-Ports.

 

On the other side of the AXI Mem Interconnect there are TREE slave ports. The first two are connected to the data- (M_AXI_DC) and instruction-buses (M_AXI_IC) of the Microblaze.

The third is connected to a 64Bit bus master component (HLS block).

 

Now my problem:

 

How to map address spaces in the address map correctly?

 

The MB has only a 32bit address view. So I am forced to define 2 32bit address regions for the memory modules.

I selected

* 0x4000 0000 .. 0x7fff fff for module#1 (1GByte of Module#1)

* 0x8000 0000 .. 0xffff ffff for module#2 (2GByte of Module#2)

 

My 64bus master component shall be able to access the full 8GB of both modules but I am forced to select the same memory windows there as I have with the microblaze ...

 

Additionally: I have to select a kind of basis address in the software driver (running on the microblaze) for the bus master component (which I set to 0x0000 0000)´to get access to the full range) but I miss to provide a kind of 64bit base address because I have a 64bit address space ...

Or do I have a misunderstanding regarding the base address ?

 

Does anyone have experience here ?

Any hint really appreciated :-(

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Adventurer
Adventurer
14,417 Views
Registered: ‎09-25-2015

Re: driving a 64bit address bus master with the 32bit address microblaze

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*** Topic is solved ***

 

There is a bug in the HLS Bus Master generation (in the VHDL code related to the master). Obviously at Xilinx the 64bit addresses are not tested in real 64bit environments but only with 4GB addresses. My case revealed that accessing addresses above 4GB were not possible.

A Change Request @ Xilinx s now registered: #932618

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5 Replies
Adventurer
Adventurer
9,030 Views
Registered: ‎09-25-2015

Re: driving a 64bit address bus master with the 32bit address microblaze

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Update:

The function

XSetmem_Set_addrMaster( &gSetmemInstancePtr, 0x123456789abcdef0 );

which is a generic function from automated driver generation accept now 64-bit addresses (the last value). I missed the driver regeneration after changing to 64-bit addresses.

But: it still does not work.

 

The addresses on the AXI bus show only the lower 32-bits of this upper value (0x123456789abcdef0). The upper 32bit are always zero :-(

 

To me it looks like a bug as I definitly see that the 64-bit address is written by the driver (value splitted into two 32bit values and written to the registers), but the module (setmem in my case) does not see it. It sees only 0x9abcdef0.

2015-12-04 Bus shows only half of address.png
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Adventurer
Adventurer
8,927 Views
Registered: ‎09-25-2015

Re: driving a 64bit address bus master with the 32bit address microblaze

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OK - Next update (for those being interested):

The problem in 64bit addressing lies in the different address busses I have. I have the

* "bus master bus" with which I want to transfer big chunks of data and the

* "control bus" which gives me control over return value, configuration and function parameters

 

Look at the source code

 

int setMem(
	unsigned char value,
	volatile unsigned char *addrMaster,
	int size )
{
#pragma HLS INTERFACE s_axilite port=size bundle=CTRL_BUS
#pragma HLS INTERFACE m_axi depth=100 port=addrMaster bundle=MASTER_BUS
#pragma HLS INTERFACE s_axilite port=addrMaster bundle=CTRL_BUS
#pragma HLS INTERFACE s_axilite port=value bundle=CTRL_BUS
#pragma HLS INTERFACE s_axilite port=return bundle=CTRL_BUS

	if ( size < MAX_TRANSFER_SIZE )
	{
		for ( int idxMemAddr = 0; idxMemAddr < size; idxMemAddr++ )
		{
			addrMaster[ idxMemAddr ] = value;
		}
		return 0x00000000;
	}
	else
	{
	    return 0xaabbccdd;
	}
}

I have two bundles of busses "CTRL_BUS" and "MASTER_BUS".

When now the solution in Vivado HLS is configured for 64bit addresses ("Solution settings/Add/config_interface" - see blow)

the configuration is only applied to the CONFIG AXI BUS and not the BUS Master component.

(This I have verified by looking into the relevant generated VHDL files.)

 

==> I am about to try to extend the 64bit address bus behaviour to the bus master component now ... stay tuned. Or has someone NOW a solution for me ? would be pretty nice!!!

 

 

HLS Config 64BitAddr.PNG

 

 

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Moderator
Moderator
8,843 Views
Registered: ‎04-17-2011

Re: driving a 64bit address bus master with the 32bit address microblaze

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Your MASTER_BUS is getting inferred with a 64-bit address right?
|m_axi_MASTER_BUS_AWADDR | out | 64| m_axi | MASTER_BUS | pointer |
|m_axi_MASTER_BUS_ARADDR | out | 64| m_axi | MASTER_BUS | pointer ??
Regards,
Debraj
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Adventurer
Adventurer
8,743 Views
Registered: ‎09-25-2015

Re: driving a 64bit address bus master with the 32bit address microblaze

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hmmm, I do not know what you mean ...

The bus master AXI bus is 64-bit. ARADDR as well as AWADDR are 64 bit. You can see this clearly in the waveform (range 63..0).

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Adventurer
Adventurer
14,418 Views
Registered: ‎09-25-2015

Re: driving a 64bit address bus master with the 32bit address microblaze

Jump to solution

*** Topic is solved ***

 

There is a bug in the HLS Bus Master generation (in the VHDL code related to the master). Obviously at Xilinx the 64bit addresses are not tested in real 64bit environments but only with 4GB addresses. My case revealed that accessing addresses above 4GB were not possible.

A Change Request @ Xilinx s now registered: #932618

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