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moretti740
Visitor
Visitor
1,941 Views
Registered: ‎11-07-2018

AXI Bram Controller: set_property expects at least one option

Hi,

My professor is using Vivado 2018.1. He sent me a project, and every single time I upgrade the AXI Bram Controller IP from 4.0 to 4.1 I can no longer run synthesis.

No other changes are done.

The project also fails when I create it 100% in Vivado 2018.3 from scratch (so, using 4.1)

 

The error message is:

Out-of-Context Module Runs

system

system_axi_bram_ctrl_0_bram_0_synth_1

[Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

 

 A little bit of investigation took me to these files, where I suspect the error appears

First the full log:

source system_axi_bram_ctrl_0_bram_0.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.ipdefs/Repositorio_IP_0'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.3/data/ip'.
WARNING: [Vivado 12-818] No files matched '/home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_bram_ctrl_0_bram_0/system_axi_bram_ctrl_0_bram_0_ooc.xdc'
ERROR: [Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

 

 

system_axi_bram_ctrl_0_bram_0.tcl

# 
# Synthesis run script generated by Vivado
# 

set TIME_start [clock seconds] 
proc create_report { reportName command } {
  set status "."
  append status $reportName ".fail"
  if { [file exists $status] } {
    eval file delete [glob $status]
  }
  send_msg_id runtcl-4 info "Executing : $command"
  set retval [eval catch { $command } msg]
  if { $retval != 0 } {
    set fp [open $status w]
    close $fp
    send_msg_id runtcl-5 warning "$msg"
  }
}
set_msg_config -id {HDL-1065} -limit 10000
set_param project.vivado.isBlockSynthRun true
set_msg_config -msgmgr_mode ooc_run
create_project -in_memory -part xc7z010clg400-1

set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.cache/wt [current_project]
set_property parent.project_path /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.xpr [current_project]
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language VHDL [current_project]
set_property board_part digilentinc.com:arty-z7-10:part0:1.0 [current_project]
set_property ip_repo_paths /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.ipdefs/Repositorio_IP_0 [current_project]
update_ip_catalog
set_property ip_output_repo /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
read_ip -quiet /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_bram_ctrl_0_bram_0/system_axi_bram_ctrl_0_bram_0.xci
set_property used_in_implementation false [get_files -all /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_bram_ctrl_0_bram_0/system_axi_bram_ctrl_0_bram_0_ooc.xdc]

# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
  set_property used_in_implementation false $dcp
}
read_xdc dont_touch.xdc
set_property used_in_implementation false [get_files dont_touch.xdc]
set_param ips.enableIPCacheLiteLoad 1

set cached_ip [config_ip_cache -export -no_bom -use_project_ipc -dir /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.runs/system_axi_bram_ctrl_0_bram_0_synth_1 -new_name system_axi_bram_ctrl_0_bram_0 -ip [get_ips system_axi_bram_ctrl_0_bram_0]]

if { $cached_ip eq {} } {
close [open __synthesis_is_running__ w]

synth_design -top system_axi_bram_ctrl_0_bram_0 -part xc7z010clg400-1 -mode out_of_context

#---------------------------------------------------------
# Generate Checkpoint/Stub/Simulation Files For IP Cache
#---------------------------------------------------------
# disable binary constraint mode for IPCache checkpoints
set_param constraints.enableBinaryConstraints false

catch {
 write_checkpoint -force -noxdef -rename_prefix system_axi_bram_ctrl_0_bram_0_ system_axi_bram_ctrl_0_bram_0.dcp

 set ipCachedFiles {}
 write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ system_axi_bram_ctrl_0_bram_0_stub.v
 lappend ipCachedFiles system_axi_bram_ctrl_0_bram_0_stub.v

 write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ system_axi_bram_ctrl_0_bram_0_stub.vhdl
 lappend ipCachedFiles system_axi_bram_ctrl_0_bram_0_stub.vhdl

 write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ system_axi_bram_ctrl_0_bram_0_sim_netlist.v
 lappend ipCachedFiles system_axi_bram_ctrl_0_bram_0_sim_netlist.v

 write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ system_axi_bram_ctrl_0_bram_0_sim_netlist.vhdl
 lappend ipCachedFiles system_axi_bram_ctrl_0_bram_0_sim_netlist.vhdl
set TIME_taken [expr [clock seconds] - $TIME_start]

 config_ip_cache -add -dcp system_axi_bram_ctrl_0_bram_0.dcp -move_files $ipCachedFiles -use_project_ipc  -synth_runtime $TIME_taken  -ip [get_ips system_axi_bram_ctrl_0_bram_0]
}

rename_ref -prefix_all system_axi_bram_ctrl_0_bram_0_

# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef system_axi_bram_ctrl_0_bram_0.dcp
create_report "system_axi_bram_ctrl_0_bram_0_synth_1_synth_report_utilization_0" "report_utilization -file system_axi_bram_ctrl_0_bram_0_utilization_synth.rpt -pb system_axi_bram_ctrl_0_bram_0_utilization_synth.pb"

if { [catch {
  file copy -force /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.runs/system_axi_bram_ctrl_0_bram_0_synth_1/system_axi_bram_ctrl_0_bram_0.dcp /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_bram_ctrl_0_bram_0/system_axi_bram_ctrl_0_bram_0.dcp
} _RESULT ] } { 
  send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
  error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}

if { [catch {
  write_verilog -force -mode synth_stub /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_bram_ctrl_0_bram_0/system_axi_bram_ctrl_0_bram_0_stub.v
} _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}

if { [catch {
  write_vhdl -force -mode synth_stub /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_bram_ctrl_0_bram_0/system_axi_bram_ctrl_0_bram_0_stub.vhdl
} _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}

if { [catch {
  write_verilog -force -mode funcsim /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_bram_ctrl_0_bram_0/system_axi_bram_ctrl_0_bram_0_sim_netlist.v
} _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}

if { [catch {
  write_vhdl -force -mode funcsim /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_bram_ctrl_0_bram_0/system_axi_bram_ctrl_0_bram_0_sim_netlist.vhdl
} _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}


} else {


if { [catch {
  file copy -force /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.runs/system_axi_bram_ctrl_0_bram_0_synth_1/system_axi_bram_ctrl_0_bram_0.dcp /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_bram_ctrl_0_bram_0/system_axi_bram_ctrl_0_bram_0.dcp
} _RESULT ] } { 
  send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
  error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}

if { [catch {
  file rename -force /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.runs/system_axi_bram_ctrl_0_bram_0_synth_1/system_axi_bram_ctrl_0_bram_0_stub.v /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_bram_ctrl_0_bram_0/system_axi_bram_ctrl_0_bram_0_stub.v
} _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}

if { [catch {
  file rename -force /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.runs/system_axi_bram_ctrl_0_bram_0_synth_1/system_axi_bram_ctrl_0_bram_0_stub.vhdl /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_bram_ctrl_0_bram_0/system_axi_bram_ctrl_0_bram_0_stub.vhdl
} _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}

if { [catch {
  file rename -force /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.runs/system_axi_bram_ctrl_0_bram_0_synth_1/system_axi_bram_ctrl_0_bram_0_sim_netlist.v /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_bram_ctrl_0_bram_0/system_axi_bram_ctrl_0_bram_0_sim_netlist.v
} _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}

if { [catch {
  file rename -force /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.runs/system_axi_bram_ctrl_0_bram_0_synth_1/system_axi_bram_ctrl_0_bram_0_sim_netlist.vhdl /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_bram_ctrl_0_bram_0/system_axi_bram_ctrl_0_bram_0_sim_netlist.vhdl
} _RESULT ] } { 
  puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}

}; # end if cached_ip 

if {[file isdir /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.ip_user_files/ip/system_axi_bram_ctrl_0_bram_0]} {
  catch { 
    file copy -force /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_bram_ctrl_0_bram_0/system_axi_bram_ctrl_0_bram_0_stub.v /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.ip_user_files/ip/system_axi_bram_ctrl_0_bram_0
  }
}

if {[file isdir /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.ip_user_files/ip/system_axi_bram_ctrl_0_bram_0]} {
  catch { 
    file copy -force /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_bram_ctrl_0_bram_0/system_axi_bram_ctrl_0_bram_0_stub.vhdl /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.ip_user_files/ip/system_axi_bram_ctrl_0_bram_0
  }
}
file delete __synthesis_is_running__
close [open __synthesis_is_complete__ w]

 

I believe the error is located here:

 set_property used_in_implementation false [get_files -all /home/dc740/CIAA/docs/cese7co2018/Microarquitecturas/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_bram_ctrl_0_bram_0/system_axi_bram_ctrl_0_bram_0_ooc.xdc]

 

Commenting out that line seems to help, but then it fails for another reason when it fails to find an IP in the directories. For some reason I don't understand this project works fine in the 4.0 version but not in the 4.1

 

Any clue?

 

Thank you

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7 Replies
chinmays
Xilinx Employee
Xilinx Employee
1,897 Views
Registered: ‎06-27-2018

Hi @moretti740 ,

Can you please have a at AR#70722 once, the issue looks similar. Let me know if it helps.

Thanks,
Chinmay

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moretti740
Visitor
Visitor
1,873 Views
Registered: ‎11-07-2018

Hi, I'm not planning on spending any time on this. I downgraded to Vivado 2018.1 which works as expected. I'll only upgrade again if I really have no other choice in the following years.

 

I hope you can reproduce and fix it some day.

Thank you

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surajc
Moderator
Moderator
1,779 Views
Registered: ‎01-30-2019

@moretti740 ,

can you share the design files to reproduce the issue at our end

--Suraj

 

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mmechtenberg
Visitor
Visitor
1,013 Views
Registered: ‎01-20-2020

Similar problem here. 

I was able to setup a minimal board design, which recreates the issue in Vivado 2018.3 and 2019.1 with ubuntu as os.

However on Windows 10 this board design works with the mentioned Vivado versions. But i can't switch to windows as build system.

I can't share the whole project as the max file size limit is to low. Therefor a tcl script is append which generates the vivado project and board design.

 

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Hartan
Visitor
Visitor
975 Views
Registered: ‎09-25-2020

Same situation for me. I'm using Debian 10 as OS, but I can't make the BRAM Controller (Version 4.1) work properly with the "Block Memory Generator" IP... I tried using Vivado 2018.3 and 2019.1.

I tried the TCL script from @mmechtenberg, too, and can confirm that it doesn't work on my end.

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petrot
Visitor
Visitor
945 Views
Registered: ‎10-03-2018

I spent my whole afternoon on the subject, and it appears that this is a shell language issue (I have been directed towards that feeling thanks to https://www.xilinx.com/support/answers/72611.html). So before launching Vivado, just do (bash like shell) export LC_ALL="C" and this solves the problem.

Hope this helps,

Frédéric

mmechtenberg
Visitor
Visitor
910 Views
Registered: ‎01-20-2020

Thanks for your time. Your instructions worked, at least for Vivado 2018.3.

Here a small script which starts Vivado.

#!/bin/bash

cd /opt/Xilinx/Vivado/2018.3/bin/
export LC_ALL="C"

./vivado

 

One has to reset generated files associated with the bram controller, if these were generated with vivado without the mentioned modification.

On my end it is was not sufficient  to clear the output products. I don't know which files need to be regenerated. I went the easy route

and deleted the whole project and regenerated it with my project tcl script.

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