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Visitor dheerendrat
Visitor
200 Views
Registered: ‎05-07-2019

Avoid resynthesis of Block Design in Non Project mode

 Hi,

      Thanks for reading through my query. I am using a block design generated from Vivado and integrating it with my custom design in Non Project mode i.e. through a tcl script. 

I went through the followin AR https://forums.xilinx.com/t5/Vivado-TCL-Community/Block-Design-in-non-project-mode/m-p/484200#M1721 that helps me integrating the block design with the rest of my design. 

However

1.) The block design resynthesizes every time I make changes in my custom design and do a rebuild. Is there a way to avoid that?

2.) I have exported the block design generation tcl script using write_bd_tcl command so that I don't have to keep the block design source files in my version control. So I do the below in my tcl script. 

source gen_bd.tcl
generate_target all [get_files  <proj>.srcs/sources_1/bd/design_1/design_1.bd]
read_vhdl -library work [ glob <proj>.srcs/sources_1/bd/design_1/hdl/design_1.vhd ]  

Is there a check that I can place around this tcl code to avoid rebuilding the block design everytime. What should be checked for the same?

3.) I have included the wrapper file for block design in my filelist and kept it separately and do not generate it in gen_bd.tcl. Can the synthesis tool automatically locate the generated block design paths. (Sorry if it appears trivial, I am actually a newbie with Vivado)

 

Thanks

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2 Replies
Xilinx Employee
Xilinx Employee
182 Views
Registered: ‎01-30-2019

Re: Avoid resynthesis of Block Design in Non Project mode

@dheerendrat 

The feature you are looking for in all your questions is the use of IP cache 

please refer to page no 13 of the following UG896 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug896-vivado-ip.pdf#page=13

and sadly use of IP cache is not supported in Non-project mode.

--Suraj

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Visitor dheerendrat
Visitor
171 Views
Registered: ‎05-07-2019

Re: Avoid resynthesis of Block Design in Non Project mode

@surajc
Thanks for pointing me to the document. I see that you mentioned IP cache cannot be used in Non Project Mode. So, is there no way around resynthesizing the whole block design again and again? I have seen projects where a proj.xci is synthesized only once in a current database and doesn't require resynthesis, even in non-project mode. I was wondering if a similar thing must be possible for block design as well.
I will wait for more answers before closing this thread.
Thanks a lot for your inputs.

Regards
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