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Explorer
Explorer
16,944 Views
Registered: ‎11-12-2007

Block Design in non-project mode

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hi,

I am trying to use non-project flow and addin a bd_design to my project. I have a top-level.vhd which instatiates the bd-design  "design_1.bd" like this:


system_i: entity work.design_1
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) =

...

..

);

 

I can't run synth design, because Vivado can't elaborate the "design_1": ERROR: [Synth 8-493] no such design unit 'design_1'

 

I am running Vivado 2014.1.

The bd_design was saved to tcl with write_bd_tcl. My script looks like this so far: 

# STEP#0: define output directory area.
#
set outputDir ./out/output             
file mkdir $outputDir

# STEP#1: setup design sources and constraints
#
read_vhdl -library work [ glob ./src/*.vhd ]         
read_xdc [ glob ./src/*.xdc ]
set_property PART xc7z015clg485-2 [current_project]

# set ip repository path
set_property IP_REPO_PATHS ./ip_rep [current_fileset ]
update_ip_catalog

# recreate the bd_design
source setup_bd.tcl

#
# STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design
#
synth_design -top system_top -part xc7z015clg485-2 -flatten rebuilt  

 

Which step did I miss?

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1 Solution

Accepted Solutions
Explorer
Explorer
28,831 Views
Registered: ‎11-12-2007

Re: Block Design in non-project mode

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OK, I got it:

generate_target all [get_files .srcs/sources_1/bd/design_1/design_1.bd]
read_vhdl -library work [ glob .srcs/sources_1/bd/design_1/hdl/design_1.vhd ]

 

are needed. My script now looks like this:

# A Vivado script that demonstrates a very simple RTL-to-bitstream batch flow
#
# NOTE:  typical usage would be "vivado -mode tcl -source create_bft_batch.tcl" 
#
# STEP#0: define output directory area.
#
set outputDir ./out/output             
file mkdir $outputDir



# STEP#1: setup design sources and constraints
#
read_vhdl -library work [ glob ./src/*.vhd ]         
read_xdc [ glob ./src/*.xdc ]
set_property PART xc7z015clg485-2 [current_project]

# Set project properties
set obj [current_project]
set_property "default_lib" "xil_defaultlib" $obj
set_property "part" "xc7z015clg485-2" $obj
set_property "simulator_language" "Mixed" $obj
set_property "target_language" "VHDL" $obj

#set ip repository path
set_property IP_REPO_PATHS ./ip_rep [current_fileset ]
update_ip_catalog

# create the BD-Design
source setup_bd.tcl
generate_target all [get_files  .srcs/sources_1/bd/design_1/design_1.bd]
read_vhdl -library work [ glob .srcs/sources_1/bd/design_1/hdl/design_1.vhd ]  

# STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design
#
synth_design -top system_top -part xc7z015clg485-2 -flatten rebuilt    
write_checkpoint -force $outputDir/post_synth
report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
report_power -file $outputDir/post_synth_power.rpt

# STEP#3: run placement and logic optimzation, report utilization and timing estimates, write checkpoint design
#
opt_design
place_design
phys_opt_design
write_checkpoint -force $outputDir/post_place
report_timing_summary -file $outputDir/post_place_timing_summary.rpt

# STEP#4: run router, report actual utilization and timing, write checkpoint design, run drc, write verilog and xdc out
#
route_design
write_checkpoint -force $outputDir/post_route
report_timing_summary -file $outputDir/post_route_timing_summary.rpt
report_timing -sort_by group -max_paths 100 -path_type summary -file $outputDir/post_route_timing.rpt
report_clock_utilization -file $outputDir/clock_util.rpt
report_utilization -file $outputDir/post_route_util.rpt
report_power -file $outputDir/post_route_power.rpt
report_drc -file $outputDir/post_imp_drc.rpt
write_verilog -force $outputDir/bft_impl_netlist.v
write_xdc -no_fixed_only -force $outputDir/bft_impl.xdc

# STEP#5: generate a bitstream
# 
write_bitstream -force $outputDir/bft.bit

 

6 Replies
Xilinx Employee
Xilinx Employee
16,942 Views
Registered: ‎04-16-2012

Re: Block Design in non-project mode

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Hi,

 

Attach setup_bd.tcl here to debug the issue.

 

Thanks,

Vinay

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Explorer
Explorer
16,936 Views
Registered: ‎11-12-2007

Re: Block Design in non-project mode

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setup_bd.tcl is attached. It's unmodified output from write_bd_tcl.

 

I found out, that I am missing the "Generate Block Design" step. It then generate the block design and a design_1.v, which I can read with 

read_verilog [ glob .srcs/sources_1/bd/design_1/hdl/design_1.v ]

 

 

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Explorer
Explorer
28,832 Views
Registered: ‎11-12-2007

Re: Block Design in non-project mode

Jump to solution

OK, I got it:

generate_target all [get_files .srcs/sources_1/bd/design_1/design_1.bd]
read_vhdl -library work [ glob .srcs/sources_1/bd/design_1/hdl/design_1.vhd ]

 

are needed. My script now looks like this:

# A Vivado script that demonstrates a very simple RTL-to-bitstream batch flow
#
# NOTE:  typical usage would be "vivado -mode tcl -source create_bft_batch.tcl" 
#
# STEP#0: define output directory area.
#
set outputDir ./out/output             
file mkdir $outputDir



# STEP#1: setup design sources and constraints
#
read_vhdl -library work [ glob ./src/*.vhd ]         
read_xdc [ glob ./src/*.xdc ]
set_property PART xc7z015clg485-2 [current_project]

# Set project properties
set obj [current_project]
set_property "default_lib" "xil_defaultlib" $obj
set_property "part" "xc7z015clg485-2" $obj
set_property "simulator_language" "Mixed" $obj
set_property "target_language" "VHDL" $obj

#set ip repository path
set_property IP_REPO_PATHS ./ip_rep [current_fileset ]
update_ip_catalog

# create the BD-Design
source setup_bd.tcl
generate_target all [get_files  .srcs/sources_1/bd/design_1/design_1.bd]
read_vhdl -library work [ glob .srcs/sources_1/bd/design_1/hdl/design_1.vhd ]  

# STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design
#
synth_design -top system_top -part xc7z015clg485-2 -flatten rebuilt    
write_checkpoint -force $outputDir/post_synth
report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
report_power -file $outputDir/post_synth_power.rpt

# STEP#3: run placement and logic optimzation, report utilization and timing estimates, write checkpoint design
#
opt_design
place_design
phys_opt_design
write_checkpoint -force $outputDir/post_place
report_timing_summary -file $outputDir/post_place_timing_summary.rpt

# STEP#4: run router, report actual utilization and timing, write checkpoint design, run drc, write verilog and xdc out
#
route_design
write_checkpoint -force $outputDir/post_route
report_timing_summary -file $outputDir/post_route_timing_summary.rpt
report_timing -sort_by group -max_paths 100 -path_type summary -file $outputDir/post_route_timing.rpt
report_clock_utilization -file $outputDir/clock_util.rpt
report_utilization -file $outputDir/post_route_util.rpt
report_power -file $outputDir/post_route_power.rpt
report_drc -file $outputDir/post_imp_drc.rpt
write_verilog -force $outputDir/bft_impl_netlist.v
write_xdc -no_fixed_only -force $outputDir/bft_impl.xdc

# STEP#5: generate a bitstream
# 
write_bitstream -force $outputDir/bft.bit

 

Xilinx Employee
Xilinx Employee
16,922 Views
Registered: ‎09-20-2012

Re: Block Design in non-project mode

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Hi,

 

Thanks  for sharing the solution.

 

Please close the thread by marking the answer.

 

Regards,

Deepika.

Thanks,
Deepika.
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Observer klindseth
Observer
13,841 Views
Registered: ‎03-07-2008

Re: Block Design in non-project mode

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Is this script still valid in 2015.3 or are there changes required?

 

This should be in your tutorial because it includes the critical case of adding the exported block design, with presumably the Zynq CPU and all that.  Thanks to the author of this thread.  It fills a big hole in your app notes.

 

I have tried the approach of using the read_bd commands and read_ip commands, which is sort of implied in some of the documentation, but have not had any luck.  I will try this method.

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Explorer
Explorer
13,766 Views
Registered: ‎11-12-2007

Re: Block Design in non-project mode

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Yes, the script still works for me on 2015.3.
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