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Block design differs through TCL saving/generating

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Posts: 9
Registered: ‎06-08-2017

Block design differs through TCL saving/generating

[ Edited ]

Hi all,

 

I am using Vivado 2017.2 for some Artix7 devices.

 

My project involves a block design which I carefully set via all contained IP's GUI sot that it's saved and validated successfully.

I then use a script to save my project including the block design using the following TCL:

 

# Open Block Design
open_bd_design {../src/ip_gen/cmd_manager/cmd_manager.bd}

# Validate Block design
validate_bd_design

# Create Block Design generation script
write_bd_tcl -bd_folder ../src/ip_gen -force -bd_name cmd_manager {../script/vivado_bd.tcl}

# Remove the Block design to avoid error during project generation because of late Block design generation
remove_files {../src/ip_gen/cmd_manager/cmd_manager.bd}

# Create Vivado project generation script
write_project_tcl -force -no_copy_sources -paths_relative_to . -target_proj_dir ../work {../script/vivado_prj.tcl}

# Undo remove of the Block design
add_files -fileset sources_1 {../src/ip_gen/cmd_manager/cmd_manager.bd} -norecurse
update_compile_order -fileset sources_1

puts "Block Design & Project saved successfully!"

 

 

First things firt, I find some weird commands in the resulting vivado_bd.tcl that try to create address_segments for my AXI network which I didn't define (even weirder noticing they correspond to disabled connectivities in the crossbar settings). E.g:

 

  # Create address segments
  create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces axi_pcie_cpu/M_AXI] [get_bd_addr_segs axi4l_to_regs_0/interface_aximm/reg0] SEG_axi4l_to_regs_0_reg0
  create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 [get_bd_addr_spaces axi_pcie_cpu/M_AXI] [get_bd_addr_segs axi_spi_alim/AXI_LITE/Reg] SEG_axi_spi_alim_Reg # Never set it myself in the block design, plus it's disabled in crossbar connectivity
  create_bd_addr_seg -range 0x00010000 -offset 0x44A20000 [get_bd_addr_spaces axi_pcie_cpu/M_AXI] [get_bd_addr_segs axi_spi_eth/AXI_LITE/Reg] SEG_axi_spi_eth_Reg # Never set it myself in the block design, plus it's disabled in crossbar connectivity
  create_bd_addr_seg -range 0x00010000 -offset 0x44A50000 [get_bd_addr_spaces axi_pcie_cpu/M_AXI] [get_bd_addr_segs axi_spi_tp/AXI_LITE/Reg] SEG_axi_spi_tp_Reg # Never set it myself in the block design, plus it's disabled in crossbar connectivity
  create_bd_addr_seg -range 0x00010000 -offset 0x44A30000 [get_bd_addr_spaces axi_pcie_cpu/M_AXI] [get_bd_addr_segs axi_spi_zero/AXI_LITE/Reg] SEG_axi_spi_zero_Reg # Never set it myself in the block design, plus it's disabled in crossbar connectivity
  create_bd_addr_seg -range 0x00010000 -offset 0x44A40000 [get_bd_addr_spaces axi_pcie_cpu/M_AXI] [get_bd_addr_segs xadc/s_axi_lite/Reg] SEG_xadc_Reg # Never set it myself in the block design, plus it's disabled in crossbar connectivity
  create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces spi_ctrl_alim/interface_aximm] [get_bd_addr_segs axi4l_to_regs_0/interface_aximm/reg0] SEG_axi4l_to_regs_0_reg0
  create_bd_addr_seg -range 0x00010000 -offset 0x44A40000 [get_bd_addr_spaces spi_ctrl_alim/interface_aximm] [get_bd_addr_segs axi_spi_alim/AXI_LITE/Reg] SEG_axi_spi_alim_Reg
  create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces spi_ctrl_eth/interface_aximm] [get_bd_addr_segs axi4l_to_regs_0/interface_aximm/reg0] SEG_axi4l_to_regs_0_reg0
  create_bd_addr_seg -range 0x00010000 -offset 0x44A30000 [get_bd_addr_spaces spi_ctrl_eth/interface_aximm] [get_bd_addr_segs axi_spi_eth/AXI_LITE/Reg] SEG_axi_spi_eth_Reg
  create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces spi_ctrl_tp/interface_aximm] [get_bd_addr_segs axi4l_to_regs_0/interface_aximm/reg0] SEG_axi4l_to_regs_0_reg0
  create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 [get_bd_addr_spaces spi_ctrl_tp/interface_aximm] [get_bd_addr_segs axi_spi_tp/AXI_LITE/Reg] SEG_axi_spi_tp_Reg
  create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces spi_ctrl_zero/interface_aximm] [get_bd_addr_segs axi4l_to_regs_0/interface_aximm/reg0] SEG_axi4l_to_regs_0_reg0
  create_bd_addr_seg -range 0x00010000 -offset 0x44A20000 [get_bd_addr_spaces spi_ctrl_zero/interface_aximm] [get_bd_addr_segs axi_spi_zero/AXI_LITE/Reg] SEG_axi_spi_zero_Reg
  create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces xadc_ctrl_0/interface_aximm] [get_bd_addr_segs axi4l_to_regs_0/interface_aximm/reg0] SEG_axi4l_to_regs_0_reg0
  create_bd_addr_seg -range 0x00010000 -offset 0x44A50000 [get_bd_addr_spaces xadc_ctrl_0/interface_aximm] [get_bd_addr_segs xadc/s_axi_lite/Reg] SEG_xadc_Reg
  create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces AXI_DEBUG] [get_bd_addr_segs axi4l_to_regs_0/interface_aximm/reg0] SEG_axi4l_to_regs_0_reg0
  create_bd_addr_seg -range 0x00010000 -offset 0x44A40000 [get_bd_addr_spaces AXI_DEBUG] [get_bd_addr_segs axi_spi_alim/AXI_LITE/Reg] SEG_axi_spi_alim_Reg
  create_bd_addr_seg -range 0x00010000 -offset 0x44A30000 [get_bd_addr_spaces AXI_DEBUG] [get_bd_addr_segs axi_spi_eth/AXI_LITE/Reg] SEG_axi_spi_eth_Reg
  create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 [get_bd_addr_spaces AXI_DEBUG] [get_bd_addr_segs axi_spi_tp/AXI_LITE/Reg] SEG_axi_spi_tp_Reg
  create_bd_addr_seg -range 0x00010000 -offset 0x44A20000 [get_bd_addr_spaces AXI_DEBUG] [get_bd_addr_segs axi_spi_zero/AXI_LITE/Reg] SEG_axi_spi_zero_Reg
  create_bd_addr_seg -range 0x00010000 -offset 0x44A50000 [get_bd_addr_spaces AXI_DEBUG] [get_bd_addr_segs xadc/s_axi_lite/Reg] SEG_xadc_Reg

I thought it'd be ignored and then tried to re-generate my profiler via this TCL:

 

 

# Ignore the origin_dir variable to improve portability
set ::origin_dir_loc "."

# Create Vivado project
source ../script/vivado_prj.tcl

# Update IP catalog depending on new project settings
update_ip_catalog -rebuild

# Unset because origin_dir workaround must not be used with the Block design
unset ::origin_dir_loc

# Create Block Design
source ../script/vivado_bd.tcl

# Beautify the Block Design
regenerate_bd_layout
regenerate_bd_layout -routing
save_bd_design

# Update the complete project compile order
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1

puts "Project & Block Design created successfully!"

 

The project is apparently well generated except some details in the block design. When validating it, I get critical warnings about address overlaping with an address segment which I didn't define (appearing in the weird vivado_bd.tcl):

 

 

[BD 41-1353] </axi_spi_tp/AXI_LITE/Reg> is mapped at disjoint segments in master </axi_pcie_cpu/M_AXI/SEG_axi_spi_tp_Reg> at <0x44A50000 [64k]> and in master </AXI_DEBUG/SEG_axi_spi_tp_Reg> at <0x44A10000 [64k]>. It is illegal to have the same peripheral mapped to different addresses within the same network. Peripherals must either be mapped to the same offset in all masters, or to addresses that are apertures of each other to contiguous addresses that can be combined into a single aligned address with a range that is a power 2
[BD 41-1354] Segment </axi_pcie_cpu/M_AXI/SEG_axi_spi_tp_Reg> at 0x44A50000 [64k] overlaps with </xadc_ctrl_0/interface_aximm/SEG_xadc_Reg> at <0x44A50000 [64k]> in the same network

According to the original project this generated one is from, I should have no critical warning at all, because it was fine before saving. Although disapointing, I supposed I couldn't blame the generation as it's following the TCL, so I assumed the mistake was introduced by the saving action which creates all these TCL files. I started by verifying the crossbar connectivity matrix in the vivado_bd.tcl and it seems to be correct. However, I'm surprised that the Address Editor suggests an address between axi_pcie_cpu and axi_spi_tp although this link is supposed to be disabled in the crossbar matrix.

 

I then removed the additional 5 unexpected lines of address_segments and re generated the project. And unfortunatelly, I have another critical warning :

 

[BD 41-1356] Address block </axi_spi_tp/AXI_LITE/Reg> is not mapped into </axi_pcie_cpu/M_AXI>. Please use Address Editor to either map or exclude it.

I had a look to the Address Editor, and it is still there! Why is it still suggesting me to address things which aren't even connected? If I exclude the address it finally stops complaining, but why is it there? I had a read through all vivado_bd.tcl file trying to find out a clumsy link between these AXI, but nothing appeared to me, interfaces are fine and crossbar mapping as well. Is it possible to have an implicit stuff hidden somewhere that pushes this link ?

 

Although it's interesting to understand all Vivado's mechanism and find out how and where it introduced the error, my simple wish would be to fix this save bug because I don't fancy editing my saved tcl stuff by hand each time.