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elc_lover
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Registered: ‎09-21-2020

Error while using Xilinx DPU-TRD tcl file

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Hello all,

I created the DPU-TRD project in Vivado 2018 using provided TCL file from Xilinx without any problem (https://github.com/Xilinx/Vitis-AI/blob/master/dsa/DPU-TRD/prj/Vivado/README.md). However, since I need to use Vivado+Vitis 2020.2 for my projects I have to recreate the DPU-TRD with 2020.2 version. I followed the steps mentioned in the Xilinx documentation as the following:

%export TRD_HOME =<Vitis AI path>/DPU_TRD
% source <Vivado install path>/Vivado/2020.2/settings64.sh
% cd $TRD_HOME/prj/Vivado

% vivado -source scripts/trd_prj.tcl

 

 I get the following error. Can you please help me with the issue?

dpu-trd_error.png

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elc_lover
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Registered: ‎09-21-2020

I found the solution. Just in case someone else encounter the same problem, I am writing the solution here as well. The problem is despite I added the ZCU102 board to the Vivado 2020.2, somehow the source files for this board was missing in the board directory of Vivavo. So I had to download them manually from GitHub and copy to the proper path

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elc_lover
Visitor
Visitor
470 Views
Registered: ‎09-21-2020

I found the solution. Just in case someone else encounter the same problem, I am writing the solution here as well. The problem is despite I added the ZCU102 board to the Vivado 2020.2, somehow the source files for this board was missing in the board directory of Vivavo. So I had to download them manually from GitHub and copy to the proper path

View solution in original post

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