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chandan_e
Observer
Observer
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Registered: ‎11-06-2013

Header files with SystemVerilog typedefs

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I have a design in SystemVerilog. There are a bunch of header files that have some global SV typedefs. The usual technique I use for simulation or synthesis with non-Xilinx tools is to make a filelist with all the header files first followed by the RTL files.

 

In Vivado non-project mode, if I use "read_verilog -sv ..." in the same order as in my filelist and then use "synth_design ..." everything works fine.

 

However I'm running into a problem with running Vivado in project mode. I follow a similar procedure, but I use "add_files" to add all the header files first and set the "Verilog Header" property for them. I then use "add_files" for all the RTL files and set their type to SystemVerilog. During "update_compile_order" I get syntax errors on every typedef that I have in the header files. Changing their type to SystemVerilog doesn't help.

 

I have looked through the user guides and Google and found no solution. Any pointers to what I'm doing wrong or help to correct this problem will be deeply appreciated.

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chandan_e
Observer
Observer
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Registered: ‎11-06-2013

This is the result of Duth's suggestion to include the header files in the RTL files. The short answer is that it works correctly with all the typedefs being recognized.

 

Instead of editing each RTL file, I made a single all.sv file which `included all the files in my original filelist (including the header files). Then I used the following commands:

 

add_files -norecurse all.sv

set_property include_dirs {list of all rtl directories} [current_fileset]

 

This seems to have fixed my problem and synthesis works fine. Thanks for your help.

 

Chandan

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avrumw
Guide
Guide
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Registered: ‎01-23-2009

I have had success by setting the file as a global_include

 

set_property is_global_include true [get_files  <filename>.svh]

Avrum

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duthv
Xilinx Employee
Xilinx Employee
18,223 Views
Registered: ‎09-14-2007

What Avrum suggested will fix the problem, although I would consider that a WA.

 

All the global include does is to include the files with the file compilation. This is ashortcut to doing the right thing of putting in the `include where you use the typedefs.

 

Now since you got this to work in the command line and not in the GUI, that means we have a problem we need to investigate. Can you send the project?

 

Thanks

Duth

 

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avrumw
Guide
Guide
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Registered: ‎01-23-2009

Duth,

 

In non-project mode, the user has more control over the compile unit - all files read in with a single "read_verilog" command become part of the same compilation unit. Thus, if the definition file is the first one in the list of files read in in a read_verilog command, then the definitions become part of the $unit space in SystemVerilog, and are therefore visible to all files that are compiled in the same compilation unit.

 

However, in project mode, the compilation unit is not explicitly controlled; the tools make up a number of different compilation units depending on what kinds of file are used. Therefore, it is possible for the definition file to end up in a different compilation unit than some of the files that need it.


Similarly, the compilation order has a similar issue. In non-project mode, the user controls the compile order with the order of read_verilog commands, and also through the order of the list of files provided to each read_verilog command. Again, in project mode, the compilation order is harder to control (there are mechanisms for managing it, but they are a bit more difficult).

 

So, I don't think there is a problem other than the relatively odd way that project mode defines compilation units.

 

That being said, using a `include for the definition file at the top of each file that needs it (ideally with a `define, `ifdef  that prevents it from being read twice in the same compilation unit) is the cleaner solution.

 

`ifndef MY_H_INCLUDED
  `define MY_H_INCLUDED

<all definitions, whether in a package or not, go here>

`endif

 

Avrum

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duthv
Xilinx Employee
Xilinx Employee
18,210 Views
Registered: ‎09-14-2007

Yes absolutely!

 

The way we have implemented this is to have all the Verilog files in one compile unit and all the SystemVerilog files in another compile unit.

 

The right fix is to ensure that you are putting the `include in the files before you use it. This is the LRM complaint method.

 

You are absolutely correct if you manually go about doing this with managing the compile units manually instead of putting it in all the right files, then there will be a difference. Even more reason to do this in the HDL itself :)..

 

The example you included is perfect as this is the cleanest way to do this and will be portable to any tool out there..

 

Thanks

Duth

 

 

 

 

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chandan_e
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Registered: ‎11-06-2013

Thank you so much for the suggestions.

 

Avrum's suggestion to tag all the SV header files as global include files didn't work. To be able to do this, I have to add_files the header files and that automatically puts them in the "Compile Order" list which causes the problem (it appears that each header file is automatically compiled separately.)

 

I did consider your suggestion to be more LRM compliant by actually including the header files where they are required. Unfortunately there are almost 100 files, the code is altready working in another vendor's device (we're trying to migrate to Xilinx :-) and I am loath to "fix" something that isn't broken. However, I will try it and post the results here.

 

Regarding your request to see the project files, there is too much proprietary stuff which I cannot post here.

 

Thanks Avrum and Duth.

 

Regads,

Chandan

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duthv
Xilinx Employee
Xilinx Employee
18,194 Views
Registered: ‎09-14-2007

Hi Chandan,

 

It is very odd that Avrum's suggestion did not work. While it is not the best, that is our answer for ensuring you dont have to worry about putting it in all the files.

 

It seems that something else is going on here. 

 

Please keep us posted on your experiments and if at all you can share this or a test case, we would be very interested in seeing it.

 

Thanks

Duth

 

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chandan_e
Observer
Observer
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Registered: ‎11-06-2013

This is the result of Duth's suggestion to include the header files in the RTL files. The short answer is that it works correctly with all the typedefs being recognized.

 

Instead of editing each RTL file, I made a single all.sv file which `included all the files in my original filelist (including the header files). Then I used the following commands:

 

add_files -norecurse all.sv

set_property include_dirs {list of all rtl directories} [current_fileset]

 

This seems to have fixed my problem and synthesis works fine. Thanks for your help.

 

Chandan

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duthv
Xilinx Employee
Xilinx Employee
18,189 Views
Registered: ‎09-14-2007

Perfect!

 

Thanks for letting us know!

 

-Duth

 

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helmutforren
Scholar
Scholar
7,923 Views
Registered: ‎06-23-2014
Could one of you please be so kind as to look at my post about a different problem with SystemVerilog, includes, and typedefs? To be more efficient, perhaps start by reading my entry dated "‎03-28-2017 07:42 AM". The post is here: https://forums.xilinx.com/t5/Synthesis/Error-Include-behaves-differently-between-Simulation-and/m-p/757139#M21102
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