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Participant bradselw
Participant
10,495 Views
Registered: ‎03-01-2013

How to specify which LUT pin a route through uses?

In Vivado, I am trying to manually route a signal to a DFF in a slice (Kintex7). The D6LUT and CARRY4 BELs are being used, so I need to route through the D5LUT to reach the FF's D pin. The net I'm routing comes in through the site's D1 pin, which is connected to the D5LUT's A1 pin. Vivado does make a route through when I place the cell, but for some reason it only routes through the A5 pin on the D5LUT - I need some way to change it to the A1 pin. Any suggestions?

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2 Replies
Xilinx Employee
Xilinx Employee
10,472 Views
Registered: ‎03-24-2008

Re: How to specify which LUT pin a route through uses?

What you want is a LOCK_PINS constraint - very similar to what you did in ISE.

 

Have a look at UG 903 on using constraints with Vivado:

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug903-vivado-using-constraints.pdf

 

Greg Daughtry
Vivado Product Marketing Director, Xilinx, Inc.
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Visitor audiodane
Visitor
8,161 Views
Registered: ‎09-26-2012

Re: How to specify which LUT pin a route through uses?

Do you mean to apply the LOCK_PINS constraint to the DFF itself, here? I have a similar situation in that the LUT itself (using the O6 output) has an equation to use one input, and another input is being used to pass-through to the DFF input. The LUT constraint doesn't even SEE the DFF pass-through input, since it's not a part of the truth table. Can you give us an example of how to constrain which input a LUT5 pass-through uses en-route to a DFF?

cheers,
..dane
http://audiodane.dandk.org
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