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Visitor
Visitor
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Registered: ‎08-12-2018

I am looking for a way to register reporting

For example, in the following exampe1 code, find the rEn register
I want to replace it with example2 code.
I am looking for a way to print out how many destnation registers are connected in the source register order.

 

module example1(Rst, Clk, En, InData, OutData0, OutData1, OutData2, OutData3);
input Rst, Clk;
input [1:0] En;
input [255:0] InData;
output [255:0] OutData0, OutData1, OutData2, OutData3;

reg [255:0] OutData0, OutData1, OutData2, OutData3;
reg [1:0] rEn;
wire OrEn, AndEn, XorEn, XnorEn;

always @(posedge Clk or negedge Rst)
begin
   if(~Rst)
      rEn <= 0;
   else
      rEn <= En;
end
assign OrEn   = rEn[0]|rEn[1];   
assign AndEn  = rEn[0]&rEn[1];   
assign XorEn  = rEn[0]^rEn[1];   
assign XnorEn = rEn[0]~^rEn[1];   

always @(posedge Clk or negedge Rst)
begin
   if(~Rst)begin
      OutData0 <= 0;
      OutData1 <= 0;
      OutData2 <= 0;
      OutData3 <= 0;
   end
   else begin
      if(OrEn)
         OutData0 <= InData;
      if(AndEn)
         OutData1 <= InData;
      if(XorEn)
         OutData2 <= InData;
      if(XnorEn)
         OutData3 <= InData;
   end
end
endmodule

module example2(Rst, Clk, En, InData, OutData0, OutData1, OutData2, OutData3);
input Rst, Clk;
input [1:0] En;
input [255:0] InData;
output [255:0] OutData0, OutData1, OutData2, OutData3;

reg [255:0] OutData0, OutData1, OutData2, OutData3;
(* keep="true" *)reg [1:0] rEn0, rEn1, rEn2, rEn3;
wire OrEn, AndEn, XorEn, XnorEn;

always @(posedge Clk or negedge Rst)
begin
   if(~Rst)begin
      rEn0 <= 0;
      rEn1 <= 0;
      rEn2 <= 0;
      rEn3 <= 0;
   end
   else begin
      rEn0 <= En;
      rEn1 <= En;
      rEn2 <= En;
      rEn3 <= En;
   end
end
assign OrEn   = rEn0[0] | rEn0[1];   
assign AndEn  = rEn1[0] & rEn1[1];   
assign XorEn  = rEn2[0] ^ rEn2[1];   
assign XnorEn = rEn3[0]~^ rEn3[1];   

always @(posedge Clk or negedge Rst)
begin
   if(~Rst)begin
      OutData0 <= 0;
      OutData1 <= 0;
      OutData2 <= 0;
      OutData3 <= 0;
   end
   else begin
      if(OrEn)
         OutData0 <= InData;
      if(AndEn)
         OutData1 <= InData;
      if(XorEn)
         OutData2 <= InData;
      if(XnorEn)
         OutData3 <= InData;
   end
end
endmodule

 

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Moderator
Moderator
391 Views
Registered: ‎11-04-2010

Example tcl commands for you to export the destination register in the netlist:

join [all_fanout -endpoints_only -only_cells -flat [get_nets -of [get_pins XXX/Q]]] \n

"XXX" is the name of the source register

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Visitor
Visitor
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Registered: ‎08-12-2018

I tried the following tcl script.
join [all_fanout -endpoints_only -only_cells -flat [get_nets -of [get_pins */Q]]]
I couldn't find the rEn register

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Moderator
Moderator
374 Views
Registered: ‎11-04-2010

Please open a synthesized design and run the command in TCL CONSOLE.

join [all_fanout -endpoints_only -only_cells -flat [get_nets -of [get_pins rEn /Q]]]

 

 

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Visitor
Visitor
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Registered: ‎08-12-2018

We are looking for a register with as many endpoints as the rEn signal.
Therefore, we are looking for the assumption that we do not know the rEn signal.
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Moderator
Moderator
278 Views
Registered: ‎11-04-2010

Could you explain your requirement with a schematic?

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