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Observer floorbalint
Observer
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Registered: ‎07-31-2017

PcsPma IP core from tcl

Hello!

I would like to use the 10G Ethernet PCS/PMA IP Core, and generate from a tcl script. This is the important part of the script I use:

 
create_ip -vlnv xilinx.com:ip:ten_gig_eth_pcs_pma:6.0 -module_name ten_gig_eth_pcs_pma_x1y17 -dir $genDir -force -verbose
set_property CONFIG.base_kr BASE-R [get_ips ten_gig_eth_pcs_pma_x1y17]
set_property CONFIG.baser32 64bit [get_ips ten_gig_eth_pcs_pma_x1y17]
# set_property CONFIG.SupportLevel 1 [get_ips ten_gig_eth_pcs_pma_x1y17]        # 1 -> Shared Logic in core, 0-> Shared Logic in example design
set_property CONFIG.SupportLevel 0 [get_ips ten_gig_eth_pcs_pma_x1y17]
set_property CONFIG.MDIO_Management false [get_ips ten_gig_eth_pcs_pma_x1y17]
set_property CONFIG.RefClk refclk0-1 [get_ips ten_gig_eth_pcs_pma_x1y17]
set_property CONFIG.Locations X1Y17 [get_ips ten_gig_eth_pcs_pma_x1y17]
set_property CONFIG.refclkrate 156.25 [get_ips ten_gig_eth_pcs_pma_x1y17]

generate_target {instantiation_template synthesis simulation} [get_files $genDir/ten_gig_eth_pcs_pma_x1y17/ten_gig_eth_pcs_pma_x1y17.xci]

synth_ip [get_files $genDir/ten_gig_eth_pcs_pma_x1y17/ten_gig_eth_pcs_pma_x1y17.xci]
read_verilog [glob $genDir/ten_gig_eth_pcs_pma_x1y17/synth/*.v]

synth_design -top TopModul -part xcku025-ffva1156-1-c

I want to use more GTH trasciever than four, so I use the 'Shared Logic in example design' option, and I use the files, what I found in the example design for the common block.

The synth_ip command runs properly, but I have some ERROR at the synth_design command. It said : 

 

ERROR: [Synth 8-439] module 'ten_gig_eth_pcs_pma_v6_0_11' not found [c:/Users/FPGA/Desktop/tcl_tests/pcspma_tcl2/build/gen/ten_gig_eth_pcs_pma_x1y17/synth/ten_gig_eth_pcs_pma_x1y17_block.v:390]
        Parameter C_HAS_MDIO bound to: 1'b0
        Parameter C_HAS_FEC bound to: 1'b0
        Parameter C_HAS_AN bound to: 1'b0
        Parameter C_IS_KR bound to: 1'b0
        Parameter C_GTTYPE bound to: 32'sb00000000000000000000000000000010
        Parameter C_GTIF_WIDTH bound to: 32'sb00000000000000000000000001000000
        Parameter C_NO_EBUFF bound to: 1'b0
        Parameter C_IS_32BIT bound to: 1'b0
        Parameter C_DP_WIDTH bound to: 32'sb00000000000000000000000001000000
        Parameter C_SPEED10_25 bound to: 32'sb00000000000000000000000000001010
        Parameter C_REFCLKRATE bound to: 32'sb00000000000000000000000010011100
        Parameter C_1588 bound to: 32'sb00000000000000000000000000000000
ERROR: [Synth 8-285] failed synthesizing module 'ten_gig_eth_pcs_pma_x1y17_block' [c:/Users/FPGA/Desktop/tcl_tests/pcspma_tcl2/build/gen/ten_gig_eth_pcs_pma_x1y17/synth/ten_gig_eth_pcs_pma_x1y17_block.v:59]
ERROR: [Synth 8-285] failed synthesizing module 'ten_gig_eth_pcs_pma_x1y17' [c:/Users/FPGA/Desktop/tcl_tests/pcspma_tcl2/build/gen/ten_gig_eth_pcs_pma_x1y17/synth/ten_gig_eth_pcs_pma_x1y17.v:60]
ERROR: [Synth 8-285] failed synthesizing module 'wrapperMultiplePcsPma' [C:/Users/FPGA/Desktop/tcl_tests/pcspma_tcl2/src/wrapperMultiplePcsPma.v:29]
ERROR: [Synth 8-285] failed synthesizing module 'TopModul' [C:/Users/FPGA/Desktop/tcl_tests/pcspma_tcl2/src/TopModul.v:23]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 1956.688 ; gain = 0.000
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
48 Infos, 3 Warnings, 2 Critical Warnings and 6 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Mon Feb 11 19:31:50 2019...

 

I can not find the 'ten_gig_eth_pcs_pma_v6_0_11' modul in the generated files folder.

How can I fix this problem?

 

Regards,

Balint

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