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Explorer
Explorer
402 Views
Registered: ‎05-25-2016

Possible to modify register at bitstream gen step?

Hello,

 

I've been reading around on the forums about tcl scripting build counters.  It seems that the USER_ACCESS word is a common place to do this, but has limitations.  I also see that you can run .pre and .post TCL scripts for each step of the build process.  

My question is this:  Can I use a .pre TCL script for the bitstream process so that upon starting creation of a bitstream but before anything happens I can go into the implemented design and change a register value?  It sounds like  it could be possible and this could then be used as a build counter.  I have a build counter IP in my block design I update manually with a value.  It sounds like you could use this:

set_property STEPS.WRITE_BITSTREAM.TCL.PRE {tcl_pre.tcl} [get_runs impl_1]

to append a tcl script to be bitstream step.  Is it possible to write a TCL script that can go and change a register value in HDL?  I mostly only see TCL scripts that get ports, pins and interact with timing and the build process options.  

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2 Replies
Xilinx Employee
Xilinx Employee
364 Views
Registered: ‎05-22-2018

Re: Possible to modify register at bitstream gen step?

Hi @m3atwad ,

Yes i think you can change a register value in HDL using TCL script, you can use generic. Please check below UG:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug835-vivado-tcl-commands.pdf

Thanks,

Raj

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Explorer
Explorer
343 Views
Registered: ‎05-25-2016

Re: Possible to modify register at bitstream gen step?

Hi Raj,

 

Thank you for the reply.  I have been reading through this and other documentation.  This value is 32bits (standard axi sized register) and when I look at TCL commands like get_cells I can get those working, but that value would span technically 32 registers which would be 32 individual cells.  I also noticed a lot of the calls like "set_property" are for simulation.  

What approach should I take for this?  I could use a register set in verilog or I could use a genereic/parameter like I'm using now.  I can't see to find where in the synthesized data this 32 bit value is stored.

 

Should I be able to find a constant cell/primitive somewhere in the synthesized design that holds my 32bit build counter?  I've attached my code so you can see.   All I've done is add a parameter to the standard axi wrapper that I connect to a microblaze.

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