09-20-2020 09:01 AM
I have several AXI slave interfaces written in HDL and are inferred by Vivado when I use a tcl script to create and package the IP.
For example, multiples of the following
INFO: [IP_Flow 19-5107] Inferred bus interface 'S0_AXI' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
I have 8 of such inferred AXI interfaces each using a 32-bit address so I get the following warning.
WARNING: [IP_Flow 19-3238] Range of address space is set to a full 4G (Address Block 'reg0' of Memory Map 'S0_AXI'). Consider reducing this by setting the range of the address block to a lower number, or alternatively reduce the number of bits on the address line in your HDL's top level file interface.
I know that through the GUI I'm able to modify this `range` parameter in the Memory Map and reduce it to 4KB, thus getting rid of the warning. I tested if the modification of range would yield a tcl command so that I can paste it to my tcl script and use it during IP packaging but it didn't result in one.
I also know that if I create a block design I can use the `create_bd_addr_seg` tcl command and limit the range - but AFAIU this requires a block design to be open hence not available when we initially create and package an IP.
create_bd_addr_seg -range 0x00001000 -offset 0x48000000 [get_bd_addr_spaces unit1/M_AXI] [get_bd_addr_segs unit2/S0_AXI/reg0] SEG_S0_axi_reg0
Is there a tcl command that can be used to set a parameter during IP creation and packaging (AFAIU hence no block design) so that I can get rid of the address space warning?
04-14-2021 10:10 AM
Can we not change the RTL which is the source of these warnings?
Also, can you try to use set_msg_config if RTL cannot be changed: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug835-vivado-tcl-commands.pdf
04-14-2021 11:15 AM
Thank you for your quick response.
By reducing the AXILite address size (was 32bit) to the minimal needed length (8 bit), the issue is solved.