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cyril.francois
Visitor
Visitor
1,244 Views
Registered: ‎06-15-2018

Read block design

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Hi,

 

I'm trying to create a script in Non-project mode to build my project. I'm working on vivado 2016.2.

I want to "read" my block design like read_vhdl to synthesis it.

 

Hereafter an extract of my script :
# Read Top FPGA file
read_vhdl -library work $top_sources_dir/top_zynq.vhd

# Read block design
generate_target all [get_files $lib_xilinx_dir/block_design/block_design.bd]
read_vhdl -library work $lib_xilinx_dir/block_design/hdl/block_design_wrapper.vhd

 

When I run it, it succeed to read the top_zynq.vhd but can't read the block_design.bd

 

The full script is in attachement

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prathikm
Moderator
Moderator
1,231 Views
Registered: ‎09-15-2016

Hi @cyril.francois,

 

I guess for reading one or more IPI design files read_bd can be used or scoping through write_bd_tcl can be used. UG835 (link) page. 1111 and 1742.

 

Thanks

Prathik

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prathikm
Moderator
Moderator
1,232 Views
Registered: ‎09-15-2016

Hi @cyril.francois,

 

I guess for reading one or more IPI design files read_bd can be used or scoping through write_bd_tcl can be used. UG835 (link) page. 1111 and 1742.

 

Thanks

Prathik

-----------------------------------------------------------------------------------

Don't forget to reply, kudo, and mark the appropriate post as 'accept as solution'.

-----------------------------------------------------------------------------------

View solution in original post

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