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dario_87
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Registered: ‎06-07-2018

Scripted simulation using 'export_simulation' on project with IPs

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Hello,

I have a project with an IP and I need to export a script to simulate the design on Vivado 2017.4.

I use:

export_simulation -simulator xsim -script_name run_xsim.sh -directory ./generated_sim_files_xsim -runtime 1us -force -verbose

This will generate several files including vhdl.prj, which contains the required source files list:

vhdl xpm  \
"/home/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd" \

vhdl xil_defaultlib  \
"../../../srcs/top_level.vhd" \
"../../../srcs/tb.vhd" \

nosort

My top_level includes an IP which is not listed there, therefore the simulation creates a black box and I got 'U' signals.

 

If before exporting the simulation files I run 'generate output products' ie OOC synthesis for the IP, the file list changes and includes the required simulation netlist file:

vhdl xpm  \
"/home/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd" \

vhdl xil_defaultlib  \
"../../test_exp_sim.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl" \
"../../../srcs/top_level.vhd" \
"../../../srcs/tb.vhd" \

nosort

in this case the simulation goes well.

Note that it is the 'generate outputs' command that creates the 'clk_wiz_0_sim_netlist.vhdl' file.

 

Now this implies that every time I pull the project from the repo I need to synthesize all the IPs otherwise I cannot run a simulation using scripts.

I didn't face this behavior with a block design since the export_simulation uses file 'clk_wiz_0_clk_wiz.v' which can be generated simply running 'generate targets all' without synthesis.

Is there a way to generate clk_wiz_0_sim_netlist.vhdl and have it included in vhdl.prj using export_simulation without having to run OOC synthesis on IPs?

Neither generate target all and export_ip_user_files seem to work.

 

Best regards,

Dario

 

 

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hongh
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589 Views
Registered: ‎11-04-2010

Hi, @dario_87 , 

You can generate the necessary source file of IP for simulation without synthesizing the IP with the below command: 

set_property generate_synth_checkpoint false [get_files XXX/char_fifo.xci]
generate_target all [get_files XXX/char_fifo.xci]

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2 Replies
hongh
Moderator
Moderator
590 Views
Registered: ‎11-04-2010

Hi, @dario_87 , 

You can generate the necessary source file of IP for simulation without synthesizing the IP with the below command: 

set_property generate_synth_checkpoint false [get_files XXX/char_fifo.xci]
generate_target all [get_files XXX/char_fifo.xci]

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

dario_87
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574 Views
Registered: ‎06-07-2018

Hi hongh,

this works, thank you.

Anyway I noticed that it includes 'clk_wiz_0_clk_wiz.v' and 'clk_wiz_0.v' in file vlog.prj instead of generating a vhdl netlist and adding to vhdl.prj.

That's not a problem for me but I guess it would be if you are using a vhdl only simulator.

Dario

 

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