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Newbie
Newbie
1,797 Views
Registered: ‎06-07-2018

Set mark_debug using TCL in Vivado Flow

Hi all, 

 

I want to set mark debug for various signals in my design. So, I have written an XDC file with "set_property mark_debug true <net>" statements for all the signals I need to preserve. The problem is that during synthesis, I am using a non project flow using tcl scripts, after the RTL elaboration and RTL optimization phase 1, the vivado engine parses the XDC file and some signals could not be found, due to optimizations. Is there any way to avoid the optimization phase? Or any other way to keep the original signal names?

 

Thanks in advance.

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Moderator
Moderator
1,782 Views
Registered: ‎09-15-2016

Hi @noyfris

 

set_property MARK_DEBUG true [get_nets xx ]

 

The above constraint will be applied only on the netlist signals  and have no connection with RTL elaboaration and optimization phase. The nets you need to MARK DEBUG should be selected once you open the synthesized design.

For non-project mode, after synth_design you can use start_gui command to open the Vivado GUI and further the synthesized design.

 

 

Regards
Rohit
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Moderator
Moderator
1,723 Views
Registered: ‎09-15-2016

Hi @noyfris,

 

This topic is still open and is waiting for you.

 

If your question is answered and/or your issue is solved, please mark the appropriate response that resolved your issue as Accepted Solution. This way, the topic can be completed then. If this is not solved/answered, please reply in the thread.

 

Prathik
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Xilinx Employee
Xilinx Employee
1,701 Views
Registered: ‎10-19-2011

Hi @noyfris,

 

as the signals are already optimised out in synthesis, you need to tell the synthesis to keep the signal names.

The Tcl commands shown only work on a read in netlist, which you would get first after a synthesis.

You would have to put the MARK_DEBUG into your HDL code for the synthesis tool to see it.

For syntax examples please have a look at ug908, v2018.1, page 116/117.

 

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Moderator
Moderator
1,606 Views
Registered: ‎11-04-2010

Hi, @noyfris ,
You should first check the reason why the signals are removed during synthesis.
Have they been used finally to the FPGA output ports?
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