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Explorer
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Registered: ‎01-15-2019

Verilog Wrapper for VHDL entity

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Hi All,

 

Is there a way to generate a Verilog Wrapper for the VHDL entity using TCL scripts (or another way within Vivado)?

I know there is write_template utility in the TCL Store, but it generates seperately the stub and instance template.

Is there a similar utility for the a wrapper generation (instance of the VHDL Entity inside of the Verilog module)?

Thank you!

 

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Explorer
Explorer
1,182 Views
Registered: ‎07-18-2018

Re: Verilog Wrapper for VHDL entity

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@ldm.eth,

 

If you have a VHDL entity, you can just declare it like a verilog module. You just need to make sure that the ports all match. The only time you will get into trouble is if the VHDL module uses datatypes or generics defined in a package file.

If that is the case, you will need to make a VHDL wrapper for your VHDL file that interfaces with normal data types such that the level above it doesn't need the package.

But lets say you have a VHDL module:

COMPONENT fifo
  PORT (
    clk : IN STD_LOGIC;
    srst : IN STD_LOGIC;
    din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
    wr_en : IN STD_LOGIC;
    rd_en : IN STD_LOGIC;
    dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
    full : OUT STD_LOGIC;
    empty : OUT STD_LOGIC
  );
END COMPONENT;

You can just use it in a verilog file like:

fifo FIFO_INST (
  .clk(clk),     
  .srst(srst), 
  .din(din),
  .wr_en(wr_en),
  .rd_en(rd_en),
  .dout(dout),
  .full(full),
  .empty(empty)
);

And vivado will (Assuming all the names and ports match correctly) will have it sit below your Verilog Module just as if it was written in verilog.

Again, the only time you get in trouble is if you have a VHDL package with your own datatypes or constants that don't allow you to interface.

 

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Registered: ‎01-22-2015

Re: Verilog Wrapper for VHDL entity

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@ldm.eth 

It is possible to instantiate VHDL into Verilog and Verilog into VHDL.  See UG901 on about page 279 for details.

Mark

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Explorer
Explorer
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Registered: ‎07-18-2018

Re: Verilog Wrapper for VHDL entity

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@ldm.eth,

 

If you have a VHDL entity, you can just declare it like a verilog module. You just need to make sure that the ports all match. The only time you will get into trouble is if the VHDL module uses datatypes or generics defined in a package file.

If that is the case, you will need to make a VHDL wrapper for your VHDL file that interfaces with normal data types such that the level above it doesn't need the package.

But lets say you have a VHDL module:

COMPONENT fifo
  PORT (
    clk : IN STD_LOGIC;
    srst : IN STD_LOGIC;
    din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
    wr_en : IN STD_LOGIC;
    rd_en : IN STD_LOGIC;
    dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
    full : OUT STD_LOGIC;
    empty : OUT STD_LOGIC
  );
END COMPONENT;

You can just use it in a verilog file like:

fifo FIFO_INST (
  .clk(clk),     
  .srst(srst), 
  .din(din),
  .wr_en(wr_en),
  .rd_en(rd_en),
  .dout(dout),
  .full(full),
  .empty(empty)
);

And vivado will (Assuming all the names and ports match correctly) will have it sit below your Verilog Module just as if it was written in verilog.

Again, the only time you get in trouble is if you have a VHDL package with your own datatypes or constants that don't allow you to interface.

 

View solution in original post

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