06-10-2020 09:52 PM
Updating a project from Vivado 2019.2 to 2020.1
Custom IP input clocks now appear to require the FREQ_HZ parameter set, where they were previously inferred.
The Xilinx XADC_Wizard IP the configured DCLK frequency does not change the FREQ_HZ setting of the dclk port
I have my IP configured for a 125 MHz clock and connected to a 125MHz clock but still get the error:
[BD 41-238] Port/Pin property FREQ_HZ does not match between /XADC/xadc_wiz_0/dclk_in(100000000) and /clk_and_reset/clk_wiz_0/clk_out1(125000000)
I cannot change this for the IP. I have tried re-creating both the clock wizard and the XADC wizard but the error persists.
For my Custom IP I can change the parameter from the default of 100 MHz but this is undesirable, FREQ_HZ is only supposed to be required for output clocks.
Any help is appreciated
06-18-2020 06:08 PM
I'll pile on and report the same error with 2020.1:
ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /m_axis_xadc(125000000) and /xadc_wiz_0/M_AXIS(100000000) ERROR: [BD 41-238] Port/Pin property FREQ_HZ does not match between /xadc_wiz_0/m_axis_aclk(100000000) and /aclk(125000000) ERROR: [BD 41-238] Port/Pin property FREQ_HZ does not match between /xadc_wiz_0/s_axis_aclk(100000000) and /aclk(125000000)
06-24-2020 02:51 AM
Can you provide a test case?
06-24-2020 08:06 PM
I was not able to reproduce the error in a new project created in 2020.1 however the following project created in 2019.2 then upgraded to 2020.1 reproduced the error:
ERROR: [BD 41-238] Port/Pin property FREQ_HZ does not match between /xadc_wiz_0/dclk_in(100000000) and /clk_wiz_0/clk_out1(125000000)
ERROR: [BD 41-1031] Hdl Generation failed for the IP Integrator design /home/alex/gitrepo/Example_FPGA/xadc_clk_freq_test2/xadc_clk_freq_test.srcs/sources_1/bd/design_1/design_1.bd
ERROR: [Common 17-39] 'generate_target' failed due to earlier errors.
06-28-2020 02:49 AM
Would you try @vortex1601 's solution - deleting and rebuilding the block design?
06-28-2020 09:46 PM
Deleting and replacing the XADC Wizard instance did not work for me in the main project I have this issue with.
Re-building the block design is not a solution for that main project. The block design is huge and I don't have a TCL script to re-create it, I need to have 2020.1 automatically update the file