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gauthier_auvray
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Registered: ‎02-19-2020

flow tcl script

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Hi,

I use Vivado in batch mode with a tcl script that launch the different steps of the flow.

I am facing an issue with constraints files.

I would like to do the following:

1. Create project (toplevel, adding source files...) : OK

2. Add timing constraints file to constrs_1 : OK : add_files -fileset constrs_1 [glob $PrjDir/pr/def/$Target/timing_constraints.sdc ]

3. run synthesis: OK : launch_runs  synth_1; wait_on_run synth_1

4. Open synthesis run : OK : open_run synth_1

5. Then I source a tcl script that set IO constraints (pins, properties...)

6. Now I would like to create a toplevel.xdc which contains all IO constraints and add it to constrs_1. This is where I don't find solution. I also would like to keep my timing constraints file intact so that before launching implementation I have two files in constrs_1: timing_constraints.sdc and toplevel.xdc

7. Run implementation: OK : launch_runs impl_1 -to_step write_bitstream; wait_on_run impl_1 

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gauthier_auvray
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Registered: ‎02-19-2020

Hi,

Creating the directory is the solution.

Thanks,

 

Gauthier

View solution in original post

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surajc
Xilinx Employee
Xilinx Employee
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Registered: ‎01-30-2019

Hi @gauthier_auvray 

For 6 you can use the following tcl commands: ( assuming directory [pwd]/<proj_name>/<proj_name>.srcs/constrs_1/new is already created )

 

close [ open [pwd]/<proj_name>/<proj_name>.srcs/constrs_1/new/toplevel.xdc w ]
add_files -fileset constrs_1 [pwd]/<proj_name>/<proj_name>.srcs/constrs_1/new/toplevel.xdc
set_property used_in_synthesis false [get_files  [pwd]/<proj_name>/<proj_name>.srcs/constrs_1/new/toplevel.xdc]
set_property target_constrs_file [pwd]/<proj_name>/<proj_name>.srcs/constrs_1/new/toplevel.xdc [current_fileset -constrset]

 


But for this to work you need to add save_constraints -force command after te above commands so that the constraints set by the tcl in step 5 are saved in toplevel.xdc file 

Also, the above path to the new file is not generic, I used [pwd] and <project_name> just for understanding

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gauthier_auvray
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Registered: ‎02-19-2020

Hi Surajc,

Thank you for your help.

At the end of synthesis, after opening synth_1 design, .srcs folder does not exists.

As a consequence,

close [ open [pwd]/<proj_name>/<proj_name>.srcs/constrs_1/new/toplevel.xdc w ]

fails:

open_run: Time (s): cpu = 00:00:34 ; elapsed = 00:00:45 . Memory (MB): peak = 1580.469 ; gain = 1249.559
Adding constraints...
couldn't open "D:/Gauthier/NUGGETH/fpga_carte_nuggeth/dev/pr/synth_pr_test/fpga_carte_nuggeth.srcs/constrs_1/new/fpga_carte_nuggeth.xdc": no such file or directory
while executing
"open $PR_ROOTDIR/$PROJECT_TOPLEVEL.srcs/constrs_1/new/$PROJECT_TOPLEVEL.xdc w "

Regards,

Gauthier

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surajc
Xilinx Employee
Xilinx Employee
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Registered: ‎01-30-2019

Hi @gauthier_auvray 
In that case, Try creating the directory in File Explorer and then executing the command.

Let me know what is its outcome

 

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gauthier_auvray
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Registered: ‎02-19-2020

Hi,

Creating the directory is the solution.

Thanks,

 

Gauthier

View solution in original post

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